Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix

ABSTRACT

An asynchronous high density segmented programmable array logic device utilizes a programmable switch interconnection matrix to couple an array of symmetric programamble logic blocks. Each programmable logic block includes programmable output logic macrocells, programmable input/output macrocells, programmable input logic macrocells, a logic allocator and a programmable product term array. Further, the switch matrix provides centralized global routing with a fixed path independent delay. The programmable switch interconnection matrix decouples the output logic macrocells from the product term array. The logic allocator decouples the product term array from the output logic macrocells, and the I/O macrocells decouple the output logic macrocells from the package I/O pins. Thus, the architecture of this invention is easily scalable to higher density devices without compromising speed. The logic allocator steers product terms from the product term array to selected logic macrocells so that no logic product terms are permanently allocated to a specific logic macrocell. Each output logic macrocell is provided three dedicated control product terms from the programmable product term array and each I/O macrocell is provided one control product term from the programmable product term array in one embodiment. These four dedicated product terms are used to implement asynchronous applications. Each asynchronous programmable logic device of this invention is derived from the core of a programmable logic device in a family of synchronous programmable logic devices.

CROSS REFERENCE

This application is a continuation-in-part of commonly assigned U.S. patent application Ser. No. 07/699,427 entitled "A Family of Multiple Segmented Programmable Logic Blocks Interconnected by a High Speed Centralized Switch Matrix" of Mr. Om Agrawal et al. filed on May 13, 1991, which is a continuation-in-part of commonly assigned U.S. patent application Ser. No. 07/490,808 entitled "Multiple Array High Performance Programmable Logic Device Family" of Mr. Om Agrawal et al. filed on Mar. 7, 1990, which issued as U.S. Pat. No. 5,015,884 on May 14, 1991 and which Was a continuation-in-part of commonly assigned U.S. patent application Ser. No. 07/243,574 entitled "Flexible, Programmable Cell Array Interconnected By A Programmable Switch Matrix," of Mr. Om Agrawal, et al. filed on Sep. 12, 1988, which issued as U.S. Pat. No. 4,963,768 on Oct. 16, 1990 and which was a continuation-in-part of U.S. patent application Ser. No. 07/178,707, entitled "Multiple Array Customizable Logic Array," of Mr. Om Agrawal filed on Apr. 7, 1988, which issued as U.S. Pat. No. 4,931,671 on Jun. 5, 1990 and which was a continuation of U.S. patent application Ser. No. 06/717,640, entitled "Multiple Array Customizable Logic Array," of Mr. Om Agrawal, filed on Mar. 29, 1985, which issued as U.S. Pat. No. 4,742,252 on May 3, 1988, each of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to programmable, integrated circuit logic devices arranged in interrelating groups or cells of logic components and interconnectable by a user-programmable switch matrix.

2. Description of the Prior Art

Several integrated circuit packages containing a programmable chip, which permits alternative implementation of logic functions, are available. These integrated circuit packages include a plurality of pins, an architecture for interfacing the pins with the input and output leads of the circuit on the programmable chip, and another architecture for interfacing the pins and auxiliary circuits on the chip which are used to configure the programmable chip into a user selected circuit. Thus, these field programmable logic devices permit the user to program or modify the functions on an integrated circuit chip with readily available equipment so as to configure the logic function performed by the chip to that desired by the user. However, the prior art programmable logic arrays (PLAs), programmable logic devices (PLDs) and programmable gate arrays, impose constraints on the user in exchange for field programmability.

In programmable logic arrays, which are often employed for random logic networks, data routing, code converters, instruction decoders, state machines, and other functions, an array of logic AND gates and logic OR gates is provided which can be programmed for a user specified function. Each output function (output signal) of a programmable logic array is the sum (OR gate output signal) of selected products (AND gate output signals) and each product (AND gate output signal) is the product of selected input signals. Programming is accomplished by providing a programmable array or matrix between the circuit input lines and the AND gate input lines and between the output lines of the AND gates and the input lines of the OR gates, respectively. The PLA is programmed by blowing or not blowing fusible links interconnecting the conductors of the arrays.

In another embodiment, the output lines from subgroups of AND gates of the PLA are non-programmably connected to the input lines of an OR gate. A programmable array logic (PAL) device such as this is disclosed in U.S. Pat. No. 4,124,899 and incorporated herein by reference. The PAL design affords a reduction in the size of the integrated circuit chip which allows an increase in production yields and a lowering of production costs over a conventional PLA.

To further enhance the flexibility of a PAL device or a PLA device, each output signal from the OR gate array is processed by a programmable means which lets the user select either a registered output signal or a combinatorial output signal. Further, the output signal can be configured as either an active high or an active low signal. An example of an output macrocell 10, used in the prior art on an output line 11 of either a PLA or a PAL circuit, is shown in FIG. 1. Output line 11 from a programmable logic circuit is connected to a D input terminal of register 12 as well as a first input line 13 of a programmable multiplexer 19. The Q output terminal of register 12 drives a second input line 14 of multiplexer 19. The output signal from multiplexer 19, which is determined by the state of fuse 20 on line 21, drives a first input terminal of an exclusive OR gate 25. The power supply voltage is provided through a resistor 31 to the input select line 21 of multiplexer 19 and to a first end of fuse 20. The second end of fuse 20 is grounded. Accordingly, if fuse 20 is left intact, a logical zero signal is applied to input select line 21. However, if fuse 20 is blown, the signal on the input select line 21 is a logical one. Therefore, multiplexer 19 couples either the signal on line 13 or the signal on line 14 to output line 26.

The output signal from exclusive OR gate 25 is determined by fuse 23. If fuse 23 is left intact, then a logical zero is supplied to the second input terminal of exclusive OR gate 25 and the signal on line 26 is not inverted by gate 25. Conversely, if fuse 23 is blown, a logical one is provided to the second input terminal of exclusive OR gate 25 and exclusive OR gate 25 inverts the signal on line 26. Line 27 is used to tristate exclusive OR gate 25.

Output macrocell 10 also has means to provide a feedback signal to a logic circuit on line 17 of programmable multiplexer 18. Programmable multiplexer 18 has a first input line 22 connected to output line 25 of Exclusive OR gate 25 and a second input line 15 connected to Q output terminal of register 12. The signal on input select line 16 of multiplexer 18 is controlled by fuse 20, as previously described for multiplexer 19. Multiplexer 18 has three signal sources: (1) an inverted registered output signal from register 12; (2) an input signal on pin 30; or, (3) a signal from exclusive OR gate 25. If the signal on line 27 tristates exclusive OR gate 25, then an input signal on pin 30 is passed over lines 29, 22 to the first input terminal of multiplexer 18. Alternatively, the output signal of exclusive OR gate 25 is passed over lines 28, 22 to the first input terminal of multiplexer 18. Output line 17 of multiplexer 18 thus provides either an inverted or uninverted registered feedback signal, an inverted or uninverted combinatorial feedback signal, or an input signal to the logic circuit to which output macrocell 10 is connected. Output macrocell 10 is discussed in further detail in U.S. Pat. No. 4,717,912, which is incorporated herein by reference.

A disadvantage of monolithic PAL circuits is that to increase the number of input lines to the programmable AND logic array requires increasing the array size in proportion to the number of input lines. Accordingly, the size of a PAL circuit is limited by both integrated circuit technology and the cost of producing such a circuit. Also, the fuses used to program a bipolar logic array can only be programmed once and so the logic array cannot be fully tested prior to programming by the user.

The functionality of a conventional PAL device is determined by the input/output capability, the number of registers and the distribution of products terms of the device. A conventional PAL device suitable for both wide gating combinational functions, such as address decoding, multiplexing and demultiplexing, and sequential functions such as wide state machines and shift-register type functions, requires both wide input capability, i.e., a number of input lines, and a reasonably large register capability. Increasing the input capability of a conventional monolithic PAL device results in a larger array size, as described previously, which in turn results in a larger silicon die, higher cost, slower performance, and ineffective array utilization.

Erasable programmable logic devices (EPLDs) overcome the one time programmability limitation of fused logic arrays and typically use a segmented structure to enhance performance. One prior art EPLD is shown as a block diagram in FIGS. 2A, 2B and 2C (FIG. 2). The device has forty-eight input/output (I/O) pins 40, twelve dedicated input pins 41, and four pins 42 which may be used either as clock input pins or additional dedicated input pins. The signal on each I/O pin 40 is either provided to a macrocell 43 as an input signal or generated by a macrocell 43 as an output signal. Macrocells 43 are divided into three general types, a general macrocell 43, a global macrocell 60, and an enhanced macrocell 61.

General macrocell 43, as illustrated in FIG. 4, provides an input signal from I/O pin 40 to local bus 44 and programmable AND array 46 through feedback select element 47. Alternatively, a signal generated from the eight product signals on lines 49a-49h from programmable AND array 46 by I/O architecture control cell 48 is passed through buffer 49 to I/O pin 40 and through feedback select element 47 to local bus 44 and programmable AND array 46. Thus, AND array 46 is provided with either local feedback or an input signal on pin 40, but not both. In addition, programmable AND array 46 receives (1) input signals from the macrocells on the local quadrant bus 44, (2) feedback signals from global bus 45 from macrocells 60A₀ -60A₃, 60B₀ -60B₃, 60C₀ -60C₃ and 60D₀ -60D₃, and (3) signals on the sixteen dedicated input pins 41, 42 as described previously. Local macrocell programmable AND array 46 is limited to eight product terms and I/O architecture control cell 48 provides a means for generating either combinatorial or registered output signals, as previously described.

A global macrocell 60 is shown in FIG. 3. The programmable AND array 46 of global macrocell 60 is identical to programmable AND array 46 of general macrocell 43. However, the input signals to programmable AND array 46 of global macrocell 60 include both the signal from I/O pin 40, which is provided directly to global bus 45, and the signal from I/O architecture control cell 48, which is provided to local bus 44. Enhanced macrocells 61 (not shown) are utilized for critical combinatorial logic delay paths since these cells have increased speed performance through the logic array.

In another EPLD (FIGS. 5A and 5B) a programmable logic array 50 is configured as two symmetrical parts 50A, 50B with each half having 14 macrocells 51, three I/O architecture control cells 53 and one buried macrocell 52. Buried macrocell 52 is similar to group I/O architecture control cells 51 except buried macrocell 52 is not connected to an I/O pin 40 and therefore is used only to interface two macrocells with a global bus and a local bus.

In this embodiment, a selected group of macrocells, 51h-51k, 51x-51aa can share a total of sixteen additional product terms from the logic array. However, the sharing must occur between adjacent pairs of macrocells so that the additional product terms are available only to one side of the device at a given time.

The electrical programmable logic devices are implemented using CMOS technology. Also, the EPLD technology permits factory testing of all elements within the EPLD, unlike a fuse blown programmable device which can only be tested for certain configurations in the factory. The programmable connections in an EPLD typically use a CMOS floating gate architecture that is erased using a short wavelength ultraviolet (UV) light.

While an EPLD offers advantages over fuse programmable devices, the UV EPLD can be inadvertently erased if the device is left in either sunlight or fluorescent lighting. Further, the number of programmable gates, the utilization of the components in the device, and the flexibility of the device are limited by the architecture of the device. Specifically, while the devices illustrated in FIGS. 2 and 3 utilize a segmented PAL approach, each of the PAL structures is relatively large. The size of the structure results in lower performance in comparison to a smaller structure and also inefficient utilization of the array. In larger arrays, if only one or two input lines of a particular product term are used or if only one or two product terms of a particular output macrocell are used, then the remaining input lines or the remaining product terms are essentially wasted or unused.

The EPLD in FIG. 2 has 48 registers in a 68-pin package and the EPLD in FIGS. 5A and 5B has 28 registers in a 40-pin package. Therefore, the number of registers in comparison to the number of package pins is limited and consequently the functionality of these devices for registered applications is limited. Hence, both the speed and the functionality of these EPLDs are compromised by the architecture of the devices.

An alternative to a monolithic or a segmented programmable logic array is a programmable gate array wherein configurable logic blocks 70, as shown in FIG. 6A, are interfaced through switch matrices, as shown in FIG. 6B. Each configurable logic block 70 has a combinatorial logic cell 73 with four input lines 70A, 70B, 70C, 70D and two output lines 70G, 70H, a clock input line 70K, a storage element 71, and several programmable multiplexers for signal routing within the logic block. Combinational logic cell 73 uses a table look-up memory to implement Boolean logic functions of up to four variables. The programmable multiplexers utilize volatile memory cells in conjunction with pass transistors to provide configuration signals for the multiplexer. Each switch matrix 72 interfaces four horizontal metal segments with five vertical metal segments. The switches in the switch matrices are pass transistors that are controlled by a configuration bit in a volatile memory cell.

The programmable gate array circuit provides 112 flip-flops in a 68-pin PLCC package and 174 flip-flops in an 84-pin PGA package. Thus, while these devices significantly increase the number of registers over the EPLDs, described above, the devices are inefficient for wide gating applications because each configurable logic block 73 is relatively small. Therefore, an application, which requires wide gating, requires cascading in series of multiple configurable logic blocks which in turn results in reduced performance.

The semiconductor industry is consistently driven to offer higher integration, higher speed silicon devices for increased performance, lower cost system applications. For a high density PAL-like device achieving higher speed is extremely critical.

SUMMARY OF THE INVENTION

The asynchronous programmable logic device (PLD) of this invention is a high density segmented PAL-like device which gives an optimum balance between functionality, silicon die size, and performance. The high density asynchronous programmable logic device has two or more programmable logic circuits (blocks) interconnected by a switch matrix. In one embodiment, four asynchronous programmable logic blocks contained in a single integrated circuit are interconnected by a switch matrix. This segmented logic structure provides high speed performance while maintaining greater functionality than was available in prior art asynchronous programmable logic devices.

Each asynchronous programmable logic block includes a programmable logic area that has a plurality of product terms and a plurality of asynchronous programmable logic macrocells. Each asynchronous programmable logic macrocell has a plurality of dedicated control product terms for predetermined asynchronous functions. In one embodiment, the dedicated control product terms include an asynchronous preset product term, an asynchronous reset product term, and an individual clock signal. However, to enhance the user flexibility, each asynchronous programmable logic macrocell includes a programmable storage element that has access also to a plurality of synchronous clock signals. Thus, each asynchronous programmable logic block is suitable for both synchronous and asynchronous operations.

The switch matrix has a bank of programmable multiplexers for each asynchronous programmable logic block in the PLD. The input signals to the multiplexers in each bank are selected from input signals on the pins of the integrated circuit package containing the integrated circuit of this invention and output signals from the programmable logic blocks. Hence, the switch matrix functions as both an input means and a feedback means to the various logic circuits.

Each of the multiplexers in the switch matrix has configuration architecture cells which provide input select signals to the multiplexer. The input select signals configure the multiplexer so that one of the signals on an input line to the multiplexer is passed through the multiplexer to an output line of the multiplexer and the other signals on the remaining input lines are disconnected from the output line.

The asynchronous programmable logic blocks of this invention communicate with each other only through the switch matrix. Moreover, the asynchronous programmable logic blocks receive all input signals from the switch matrix. Thus, the asynchronous programmable logic blocks may be viewed as independent programmable logic devices on the same integrated circuit chip.

In one embodiment, each asynchronous programmable logic block of this invention includes a programmable logic array, a programmable logic allocator, programmable asynchronous logic macrocells, programmable input logic macrocells, and programmable I/O macrocells. The input lines to the asynchronous programmable logic block from the switch matrix drive the programmable logic array. The logic allocator is programmable so that signals from the programmable logic array are distributed to logic macrocells as required by the user of the programmable logic device.

In one embodiment, the asynchronous logic macrocells configure the signals from the logic allocator either as registered signals, latched signals, or combinatorial signals. Each asynchronous logic macrocell also has a dedicated asynchronous reset product term and a dedicated asynchronous preset product term. The output signal from an asynchronous logic macrocell is provided to an I/O macrocell and fed back to the switch matrix. The I/O macrocell selectively delivers the logic macrocell signal to an I/O pin. Alternatively, the I/O macrocell can be configured, using an output enable signal, so that the I/O pin provides an input signal to both the switch matrix and an input logic macrocell while the logic macrocell is decoupled from the I/O pin.

The logic allocator includes a multiplicity of programmable router elements. Each router element is connected to a selected number of output lines from the programmable logic array. These output lines are input lines to a logic gate. The output line from the logic gate drives the input terminal of a programmable demultiplexer. The programmable demultiplexer has a plurality of output lines, each of which is connected to the input line of one of the programmable logic macrocells. In response to an input select signal, the programmable demultiplexer passes the signal on the input line therethrough to the selected output line. Accordingly, none of the logic output lines from the programmable logic array are permanently connected to an asynchronous logic macrocell. Accordingly, when an I/O pin is used for an input pin, the asynchronous programmable logic macrocell associated with that pin may be used as a buried register, or alternatively, if the macrocell is not used, the signals from the programmable logic array are routed to other asynchronous logic macrocells so that no product terms are wasted.

While the decoupling of the asynchronous logic macrocells from the I/O pins restores the usage of the asynchronous logic macrocells as buried registers, such decoupling does not address scalability of the user design to higher density devices. The more important problem for scalability is decoupling the product term array from the macrocells so that as the number of macrocells increases, the product term array size does not increase proportionally.

The logic allocator allocates product term resources in a variable distribution among all asynchronous logic macrocells in an asynchronous programmable logic block. Thus, the logic allocator essentially decouples unused asynchronous logic macrocells from the product term array and in one embodiment allocates up to twelve product terms per asynchronous logic macrocell with minimum speed penalty.

The high speed switch matrix of this invention provides a fixed, uniform, predictable and path independent time delay for all signals that are passed through the switch matrix. Further, since the programmable logic array only receives signals from the switch matrix, the switch matrix effectively decouples the product term array from the logic macrocells, the I/O macrocells and array size.

The asynchronous programmable logic macrocells include a logic gate, that is driven by the signals on a predetermined number of output lines from the logic allocator, and a programmable element, that is driven by the output signal of the logic gate. In one embodiment, the programmable element is configurable as one of a D-type flip-flop, a T-type flip-flop, a transparent latch and a combinatorial signal path. The programmable element includes asynchronous preset and reset terminals for use when the programmable element is configured as a storage element. A dedicated product term from the programmable logic array is connected to the asynchronous preset terminal and another dedicated product term is connected to the asynchronous reset terminal.

In one embodiment, the asynchronous programmable logic macrocell of this invention also includes a means for providing one of a multiplicity of clock signals to the programmable element for use when the element is configured as a storage element. Preferably, the multiplicity of clock signals are such that each programmable logic macrocell may be clocked by a different clock signal.

The programmable input logic macrocells of this invention include a programmable storage element that is configurable as one of a D-type flip-flop and a latch. In one embodiment, the programmable logic macrocell of this invention also includes a means for providing one of a multiplicity of clock signals to the programmable storage element. Preferably, the multiplicity of clock signals is such that each programmable input logic macrocell may be clocked by a different clock signal.

Thus, programmable interconnections within the switch matrix and within each asynchronous programmable logic block are used to decouple the product-term array from the switch matrix, asynchronous logic macrocells and I/O pins. This decoupling provides greater flexibility than was available in the prior art programmable logic devices and allows the PLD of this invention to be efficiently and quickly configured for a user application. Further, the complete decoupling of the internal resources within an asynchronous programmable logic block is in sharp contrast to the prior art programmable logic device families.

In one embodiment of this invention, the high density asynchronous PLD is derived from the core of a synchronous PLD. The core of the synchronous PLD includes a switch matrix and a plurality of programmable logic blocks that each include a programmable logic array, a plurality of programmable logic macrocells and a plurality of programmable I/O macrocells. A subset of the plurality of programmable logic macrocells in a programmable logic block of the synchronous PLD, i.e., output logic macrocells, are coupled to the I/O pins by the plurality of I/O macrocells in the programmable logic block. The remaining macrocells in the plurality of programmable logic macrocells function as buried logic macrocells.

In the synchronous PLD, there are a predetermined number of product terms in the programmable logic array for each of the plurality of logic macrocells, output and buried. In the asynchronous PLD formed from the core of the synchronous PLD, the buried macrocells are configured as the input logic macrocells of the asynchronous PLD. The input logic macrocells do not receive any product terms from the programmable logic array so that the predetermined number of product terms in the programmable array for the buried logic macrocells of the synchronous PLD are configured to provide control product terms to the programmable logic macrocells and the input/output logic macrocells of the asynchronous PLD.

In one embodiment of this invention, a plurality of PLDs having a switch matrix and programmable logic blocks that include the programmable logic array, programmable logic macrocells and programmable I/O macrocells, as described above, are divided into a family synchronous and asynchronous PLDs. Each asynchronous PLD is derived from the core of the a corresponding synchronous PLD in the family.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a input/output macrocell for use with a PLA or a PAL circuit.

FIGS. 2A, 2B and 2C illustrate a prior art erasable programmable logic device.

FIG. 3 is a block diagram of a global macrocell in the prior art device illustrated in FIGS. 2A, 2B and 2C.

FIG. 4 is a block diagram of a general macrocell in the prior art device illustrated in FIGS. 2A, 2B and 2C.

FIGS. 5A and 5B are a block diagram of another prior art erasable programmable logic device.

FIGS. 6A and 6B are block diagrams of a prior art configurable logic block and a prior art switch matrix.

FIG. 7 is a block diagram of an integrated circuit according to one embodiment of the present invention.

FIG. 8 is a conceptual block diagram of another embodiment of a programmable logic device according to the principles of this invention.

FIG. 9 is a conceptual block diagram of an embodiment of a programmable logic device having complete symmetry according to the principles of this invention.

FIG. 10 is a more detailed block diagram of the programmable logic block of this invention.

FIG. 11 is a more detailed block diagram of a first embodiment of a programmable logic device in the first family of programmable logic device according to the principles of this invention.

FIGS. 12A and 12B are a more detailed block diagram of a second embodiment of a programmable logic device in the first family of programmable logic device according to the principles of this invention.

FIGS. 13A and 13B are a more detailed block diagram of a third embodiment of a programmable logic device in the first family of programmable logic device according to the principles of this invention.

FIGS. 14A and 14B are a more detailed block diagram of a first embodiment of a programmable logic device in the second family of programmable logic device according to the principles of this invention.

FIGS. 15A to 15D are a more detailed block diagram of a second embodiment of a programmable logic device in the second family of programmable logic device according to the principles of this invention.

FIGS. 16A to 16D are a more detailed block diagram of a third embodiment of a programmable logic device in the second family of programmable logic device according to the principles of this invention.

FIGS. 17A to 17D are a schematic diagram of the programmable logic block of the first embodiment in the first family of programmable logic devices according to the principles of this invention.

FIGS. 18A to 18D are a schematic diagram of the programmable logic block of the first embodiment in the second family of programmable logic devices according to the principles of this invention.

FIG. 19 illustrates a typical router element in the logic allocator of the first family of programmable logic devices of this invention.

FIGS. 20A through 20C illustrate the router elements in the logic allocator of the first embodiment in the first family of programmable logic devices of this invention.

FIG. 21 illustrates the product term steering of logic allocator 411A1 of this invention.

FIG. 22 illustrates the product term steering of logic allocator 411A2 of this invention.

FIG. 23 illustrates the product term steering of logic allocator 411A3 of this invention.

FIG. 24 illustrates a typical router element in the logic allocator of the second family of programmable logic devices of this invention.

FIGS. 25A, 25B, 25C, and 25D illustrate the router elements in the logic allocator of the first embodiment in the second family of programmable logic devices of this invention.

FIG. 26 illustrates the product term steering of the logic allocator 411B1 of this invention.

FIG. 27 illustrates the product term steering of the logic allocator 411B2 of this invention.

FIG. 28 illustrates the product term steering of the logic allocator 411B3 of this invention.

FIG. 29A is a schematic diagram of a programmable logic macrocell in the first embodiment of the first family of programmable logic devices according to the principles of this invention.

FIG. 29B is a schematic diagram of an alternative embodiment of a programmable logic macrocell in the first embodiment of the first family of programmable logic devices according to the principles of this invention.

FIG. 29C is a schematic diagram of a programmable logic macrocell in the second and third embodiments of the first family of programmable logic devices according to the principles of this invention.

FIGS. 30A through 30F illustrate possible configurations of the programmable logic macrocell in FIG. 29.

FIG. 31A is a schematic diagram of a programmable buried logic macrocell in the first embodiment of the second family of programmable logic devices according to the principles of this invention.

FIG. 31B is a schematic diagram of a programmable buried logic macrocell in the second and third embodiments of the second family of programmable logic devices according to the principles of this invention.

FIGS. 32A through 32H illustrate various configurations for the buried logic macrocell in FIG. 31.

FIG. 33 is a schematic diagram of an I/O macrocell according to the principles of this invention.

FIG. 34 is a diagram of the programmable multiplexers in switch matrix 401A1.

FIGS. 35A and 35B are an alternative representation of the input lines and the output lines to the programmable multiplexers in switch matrix 401A1 according to the principles of this invention.

FIG. 36 illustrates the signals in the 16 bands for programmable logic device 120 of this invention.

FIG. 37 is a graphical representation of the band structure used to generate the signals for the programmable 16:1 multiplexers in switch matrix 401A2 of this invention.

FIGS. 38A to 38D illustrate the input lines for each programmable 16:1 multiplexer in switch matrix 401A2.

FIG. 39 illustrates the signals in the 16 bands for programmable logic device 130 of this invention.

FIG. 40 is a graphical representation of the band structure used to generate the signals for the programmable 16:1 multiplexers in switch matrix 401A3 of this invention.

FIGS. 41A to 41D illustrate the input lines for each programmable 16:1 multiplexer in switch matrix 401A3.

FIG. 42 illustrates the signals in the 12 bands for programmable logic device 210 of this invention.

FIG. 43 is a graphical representation of the band structure used to generate the signals for the programmable 12:1 multiplexers in switch matrix 401B1 of this invention.

FIGS. 44A to 44C illustrate the input lines for each programmable 12:1 multiplexer in switch matrix 401B1.

FIG. 45 illustrates the signals in the 16 bands for programmable logic device 220 of this invention.

FIG. 46 is a graphical representation of the band structure used to generate the signals for the programmable 16:1 multiplexers in switch matrix 401B2 of this invention.

FIGS. 47A to 47O illustrate the input lines for each programmable 16:1 multiplexer in portions of switch matrix 401B2 for programmable logic blocks 402B2-1 and 402B2-8.

FIGS. 48A to 48D illustrate the input lines for each programmable 16:1 multiplexer in portions of switch matrix 401B2 for programmable logic blocks 402B2-2 and 402B2-7.

FIGS. 49A to 49D illustrate the input lines for each programmable 16:1 multiplexer in portions of switch matrix 401B2 for programmable logic blocks 402B2-3 and 402B2-6.

FIGS. 50A to 50D illustrate the input lines for each programmable 16:1 multiplexer in portions of switch matrix 401B2 for programmable logic blocks 402B2-4 and 402B2-5.

FIGS. 51A to 51D illustrate the signals in the 16 bands for each pair of programmable logic blocks in programmable logic device 230 of this invention.

FIG. 52 is a graphical representation of the band structure used to generate the signals for the programmable 16:1 multiplexers in switch matrix 401B3 of this invention.

FIGS. 53A to 53D illustrate the input lines for each programmable 16:1 multiplexer in portions of switch matrix 401B3 for programmable logic blocks 402B3-1 and 402B3-8.

FIGS. 54A to 54D illustrate the input lines for each programmable 16:1 multiplexer in portions of switch matrix 401B3 for programmable logic blocks 402B3-2 and 402B3-7.

FIGS. 55A to 55D illustrate the input lines for each programmable 16:1 multiplexer in portions of switch matrix 401B3 for programmable logic blocks 402B3-3 and 402B3-6.

FIGS. 56A to 56D illustrate the input lines for each programmable 16:1 multiplexer in portions of switch matrxx 401B3 for programmable logic blocks 402B3-4 and 402B3-5.

FIGS. 57A and 57B are a more detailed block diagram of a first embodiment of an asynchronous programmable logic device in the second family of programmable logic devices according to the principles of this invention.

FIG. 58 illustrates a typical router element in the logic allocator of the asynchronous programmable logic devices of this invention.

FIGS. 59A through 59C illustrate the router elements in the logic allocator of the asynchronous programmable logic devices of this invention.

FIG. 60 illustrates the product term steering of logic allocator 411B4 of this invention.

FIG. 61 is a schematic diagram of a programmable logic macrocell in the asynchronous programmable logic devices according to the principles of this invention.

FIG. 62 is a schematic diagram of an input logic macrocell in the asynchronous programmable logic devices according to the principles of this invention.

FIG. 63 is a schematic diagram of an input/output macrocell in the asynchronous programmable logic devices according to the principles of this invention.

In the drawings, similar items have the same number. Further, a number may represent several similar devices. For example, the base number 412 represents a group of macrocells of this invention. The number 412A1 represents a specific set of macrocells. The same component in different parts of the invention has the same base number, a dash, and then a number that differentiates the parts. Thus, macrocells 412A1-1 are macrocells in a first programmable logic block and macrocells 412A1-2 are equivalent macrocells in a second programmable logic block. Macrocell 412A1-1-6 is the sixth macrocell in the group of macrocells 412A1-1. Accordingly, a base number is a shorthand notation representing several similar devices, lines, components or other related objects.

DETAILED DESCRIPTION

FIG. 7 shows a diagram of the architecture of a multiple array programmable logic device 310 according to the present invention. The device 310 includes a first programmable array means 311 for receiving a plurality of first input terms (signals) and generating a plurality of first output terms (signals) and a second programmable array means 312 for receiving a plurality of second input terms and generating a plurality of second output terms.

First programmable array means 311 includes an AND array 316 that receives the plurality of first input terms across line 313 and preferably one clock input term across line 314 for sequential state machine functions and generates a plurality of first product terms across line 315 in response to the first input terms and the clock terms as programmed by the user. AND array 316 is preferably a field programmable AND array such as those described in the publication entitled Programmable Array Logic Handbook, published by Advanced Micro Devices, Inc. (1988), and available through Advanced Micro Devices, Inc., Sunnyvale, Calif. Of course, other embodiments of the AND array including a fixed AND array may be utilized as desired.

In first programmable array means 311, the first product terms on line 315 are supplied to an OR array 317. The OR array 317 generates a plurality of first sum-of-products terms on line 318 in response to the first product terms on line 315. The OR array may be a fixed OR array or a programmable OR array as described in the above-mentioned Programmable Array Logic Handbook.

The first sum-of-products terms on line 318 are supplied to a plurality of output cells 319 which generate output logic terms on line 320 for first programmable array means 311. Further, output cells 319 may generate feedback terms on line 321 which are fed back to the AND array 316 and utilized in the generation of the first product terms 315 as programmed by the user.

Second programmable array means 312 consists of components similar to first programmable array means 311. Thus, second programmable array means 312 includes AND array 322, which may be either fixed or programmable, and OR array 323, either fixed or programmable, and a plurality of output cells 324. Second programmable array means 312 receives as input a plurality of second input terms on line 325 and preferably one clock input term on line 326 for sequential state machine functions. The output signal of AND array 322 of second programmable array means 312 includes a plurality of second product terms 327. The output signal of OR array 323 includes a plurality of second sum-of-products terms on line 328. The plurality of second sum-of-products terms is passed through the output cells 324 and supplied as a plurality of second output terms on line 329. The output cells 324 may generate feedback terms across line 330 for supply back to AND array 322 for use in generation of the second product terms on line 327 as programmed by the user.

It should be appreciated that first programmable array means 311 and second programmable array means 312 may preferably be individually configured to include a programmable AND array with a fixed OR array, a fixed AND array with a programmable OR array, a programmable AND array with a programmable OR array or other programmable array configuration generating sum-of-products terms to facilitate conventional sum-of-products logic design.

Output cells 319 and output cells 324 for first and second programmable arrays means 311, 312, respectively, consist preferably of output cells such as those disclosed in the prior U.S. patent application entitled DYNAMICALLY CONTROLLABLE OUTPUT LOGIC CIRCUIT, Ser. No. 656,109, filed Sep. 28, 1984, or any of the output configurations disclosed in the Programmable Array Logic Handbook referred to above.

Device 310 includes a means 350 for selectively interconnecting at least subsets of the plurality of first input terms from lines 313, 314, the plurality of first output terms from lines 320, the plurality of second input terms from lines 325, 326 and the plurality of second output terms from lines 329. Means 350 for selectively interconnecting allows device 310 to be configured so that first programmable array means 311 is connected in series with second programmable array means 312, or first programmable array means 311 is connected in parallel with second programmable array means 3-2 or any combination of interconnections. A particular embodiment may interconnect subsets of the input and output terms, so that all or any portion of the plurality of first input terms, plurality of first output terms, plurality of second input terms, and plurality of second output terms may be routed as desired to provide the flexibility desired by a manufacturer.

In the embodiment shown in FIG. 7, means 350 for selectively interconnecting includes an input multiplexing means 351 (MUX I₁, MUX I₂), responsive to an input select signal on lines 352, 353, for selecting and supplying a set of signals as the plurality of first input terms or as the plurality of second input terms, from a plurality of signals. Input multiplexing means 351 (FIG. 7) selects from the plurality of signals including a first set of clock signals supplied from input pins 354, a first set of input signals externally supplied to the chip from a first set of input/output pins 355, a second set of input signals supplied from a second set of input/output pins 356 (these I/O pins are typically driven by an output signal from another device (not shown) which is similar to device 310), a second set of clock signals supplied from input pins 357, and a set of output signals, generated in response to at least a subset of the plurality of first output terms from line 320 and the plurality of second output terms from lines 329, supplied across lines 358 and 359 respectively.

The input select signal on lines 352 and 353 in the preferred embodiment is supplied as at least a subset of the first and second product terms from lines 315 and 327, respectively, or at least a subset of the first and second sum-of-products terms from lines 318 and 328, respectively, or any combination of the product terms and sum-of-products terms generated by first programmable array means 311 and second programmable array means 312.

Also, as shown in FIG. 7, the input select signal may be field programmable. Thus, FIG. 7 shows an input select signal supplied on line 390 to input multiplexer MUX I₂ from a fuse programmable signal generator 391. The fuse programmable signal generator 391 includes a fuse 392 connected from line 390 to ground and a resistor 393 connected from line 390 to a power supply voltage V_(CC). Fuse 392 is a field programmable fuse such as those described in the Programmable Array Logic Handbook, referred to above.

Input multiplexing means 351 in the preferred embodiment consists of a first input multiplexer MUX I₁, responsive to the input select signal on lines 352, for selecting a set of signals for supply as input signals on lines 313, 314, and a second input multiplexer MUX I₂, responsive to the input select signal on lines 353 or 390, for selecting a set of signals for supply as input term signals on lines 325, 326. In the embodiment shown, both first input multiplexer MUX I₁ and second input multiplexer MUX I₂ are supplied the same sets of signals from pins 354, 355, 356 and 357 for selection and supplying as input terms. The first input multiplexer MUX I₁ supplies the plurality of first input terms on lines 313, 314. The second input multiplexer MUX I₂ supplies the plurality of second input terms on lines 325, 326.

Means 350 for selectively interconnecting also includes an output multiplexing means 360, responsive to an output select signal on lines 361, 362, for selecting and supplying as output signals on lines 363 and 364, respectively, a set of signals selected from the plurality of signals selected from at least a subset of the plurality of first output terms from lines 320 and the plurality of second output terms from lines 329. The output signals on lines 363, 364 are supplied from integrated circuit device 310 externally through output drivers 365, 366 to sets of I/O pins 367, 368.

The output select signals on lines 361 and 362 can be generated from the first set of product terms on lines 315, second set of product terms on lines 327, first set of sum-of-products terms on lines 318, second set of sum-of-products terms on lines 328 or any combination of product terms and sum-of-product terms as suits the user.

Also, as shown in FIG. 7, the output select signal may be fuse programmable. Thus, FIG. 7 shows a fuse programmable signal generator 395 supplying an output select signal on line 396. The fuse programmable signal generator 395 includes a fuse 397 connected from line 396 to ground and a resistor 398 connected from line 396 to power supply voltage V_(CC). Fuse 396 is programmable as described in the above mentioned Programmable Array Logic Handbook.

Output multiplexing means 360 in the embodiment shown in FIG. 7 consists of a first output multiplexer MUX O₁ and a second output multiplexer MUX O₂. First output multiplexer MUX O₁, responsive to the output select signal on lines 361, selects a set of signals for supply as output signals on lines 363, while the second output multiplexer MUX O₂, responsive to the output select signal on lines 362 or 396, selects a set of signals for supply as output signals on lines 364.

The diagram of FIG. 7 shows four sets of I/O pins, designated 355, 356, 367 and 368. Each of these sets of I/O pins may include any number of I/O pins corresponding to the number of output signals generated on lines 363 and 364 and the number of input signals supplied from the I/O pins 355, 356 as desired. It should be noted, that the four sets of I/O pins, 355, 356, 367 and 368, are not necessarily exclusive. For instance, the set of I/O pins 367 receiving output signals across line 363 from the output multiplexer MUX O₁ is also connected to provide input signals to the input multiplexers MUX I₁ and MUX I₂ across line 358. Thus, an architecture for a device 310 according to the present invention may be laid out in which all or any subset of the I/O pins are configured to receive output signals and/or supply input signals.

Furthermore, in the preferred embodiment, the set of clock input pins 354 and the set of clock input pins 357 may include any number of clock inputs.

In one preferred embodiment, there are two clock input pins in the first set of clock input pins 354, two clock input pins in the second set of clock input pins 357, and forty I/O pins configured to provide sets of I/O pins such as those designated 355, 356, 367 and 368.

Thus it can be seen that device 310 provides total interconnectivity of the available signals and logic terms as input terms or as output terms. This allows the user the ability to configure the device 310 such that the first programmable array means 311 operates in series with the second programmable array means 312, such as by providing the output signals from line 363 as one of the sets of signals across line 358 that is selectable by the second input multiplexer MUX I₂ as at least a subset of the plurality of second input terms on line 325, 326. Of course, the second programmable array means 312 may be connected in the same manner with respect to the first programmable array means 311. Alternatively, the first programmable array means 311 and the second programmable array means 312 may be connected in parallel such that each receives the same input signals as input terms on lines 313, 314 and 325, 326, respectively, such as the input signals supplied by the set of input pins 356, and each generates a plurality of output terms across lines 320 and 329, respectively, that are selectively supplied to a set of I/O pins 367, 368.

A wide variety of other interconnection architectures can be made utilizing the means 350 for selectively interconnecting according to the present invention. For instance, a subset of the output signals from lines 363 might be supplied as a part of the set of input signals selectable by second input multiplexer MUX I₂ across line 358. Thus, a portion of the logic terms generated by second programmable logic array means 312 would be generated in response to a series connection of first programmable logic array means 311 and second programmable logic array means 312 while others of the logic terms generated by a second programmable array means 312 would be generated in parallel with or independently from logic terms generated by first programmable array means 311. In this embodiment, for instance the I/O pins 367 receiving output terms from the first programmable array means 311 might include a fewer number of pins than I/O pins 368 supplying output signals from the second programmable array means 312. As can be seen, flexibility of the present invention is extremely valuable.

An alternate preferred embodiment of a customizable logic device 310 according to the present invention is discussed in the parent U.S. Pat. No. 4,742,252 (FIG. 2 of U.S. Pat. No. 4,742,252) and incorporated herein by reference.

In FIG. 8, an integrated circuit package containing an integrated circuit chip with four programmable logic quadrants (cells) 100A, 100B, 100C, 100D and a programmable switch matrix 101 is conceptually illustrated. Each logic quadrant 100A, 100B, 100C, 100D, contains a programmable logic circuit 106A, 106B, 106C, 106D and means for coupling 105A, 105B, 105C₁, 105C₂, 105D₁, 105D₂ each logic circuit to the integrated circuit package pins. Hence, in this embodiment, as in FIG. 5, a means for coupling input signals and feedback signals, programmable switch matrix 101 (FIG. 8), with multiple programmable logic circuits is provided.

Specifically, a first selected group of integrated circuit package pins 102A are dedicated input pins 102 that are coupled by a first coupling means 111 to switch matrix 101. Coupling means 111 has programmable combinatorial and registered/latched (registered) circuit paths from input pins 102A to switch matrix 101. A second selected group of the package pins 103A, 103B, 103C are bidirectional I/O pins 103, which are coupled to four programmable logic circuits 106A, 106B, 106C, 106D by second coupling means 105A, 105B, 105C₁, 105C₂, 105D₁, 105D₂. Each of the second coupling means is programmable such that I/O pin 103 either provides an input signal to a logic quadrant or receives an output signal from a logic quadrant.

Each coupling means 105 has programmable circuitry such that either a combinatorial input path or a registered/latched input path can be established between a package pin and a logic quadrant. The combinatorial input path passes the input signal to the input line of a logic quadrant, while the registered/latched input path passes the input signal to the input terminal of a programmable storage element, and the programmable storage element, subsequently passes a signal to the input line of a logic quadrant. Similarly, each coupling means 105 includes programmable circuitry so that selected output lines from a logic circuit are coupled to an I/O pin by either a combinatorial output path or a registered/latched output path. A third group of the integrated circuit package pins 104A, 104B are global clock input pins. The global clock input pins provide synchronous clock signals to coupling means 105, 111.

Each of the four logic circuits 106A, 106B, 106C, 106D may be a PLA circuit, a PAL circuit, a NAND.NAND circuit, or a NOR.NOR circuit for example. In one embodiment, circuits 106A, 106B, 106C, 106D are programmable AND/OR logic array based PAL circuits. Each programmable AND/OR array based circuit provides 3,200 (80×40) programmable E² cells for logic flexibility. Each quadrant has twenty input lines which drive eighty product terms. Seventy-six of the product terms are used for logic functions and the other four are used for control functions, as described more completely in U.S. Pat. No. 4,963,768, entitled "Flexible, Programmable Cell Array Interconnected by A Programmable Switch Matrix," issued to Mr. Om Agrawal et al. on Oct. 16, 1990, which is incorporated herein by reference in its entirety. This segmented structure retains the benefits of a traditional PAL such as the wide input decoding, multiplexing and demultiplexing capability, without increasing the array proportionally to the number of input lines. Further, the array size and the coupling means have been selected so that the programmable logic device of this invention achieves an optimum balance of functionality, silicon die size, and performance.

The segmented structure and performance of the programmable logic device of this invention is further enhanced by a switch matrix 101. Switch matrix 101 is connected to each of the logic circuits 106A, 106B, 106C, and 106D and is coupled by means 111 to dedicated input pins 102A. Switch matrix 101, described more completely below, provides a high speed programmable means for selectively transferring signals between logic circuits 106A-106D for selectively providing input signals to logic circuits 106A-106D, and for selectively feeding signals back to a logic circuit. Hence, switch matrix 101 (FIG. 8) performs a function similar to input multiplexers I₁, I₂ (FIG. 7). Effectively, the programmable logic device of this invention is an array of four programmable logic devices interconnected by switch matrix 101.

While the invention is described in terms of a programmable AND/OR array, the programmable AND/OR array is implemented in a preferred embodiment as a NOR.NOR array that is functionally equivalent to the programmable AND/OR array described herein. As discussed more completely below, logic circuit 106A may also be a programmable OR array/fixed AND array, a PLA (programmable AND array and a programmable OR array), a NOR.NOR array, or a NAND.NAND array, for example. Accordingly, the use of a programmable AND/OR logic array is illustrative only and is not intended to limit the scope of the invention.

In the previous embodiment, the programmable logic quadrants 100A, 100B, 100C and 100D were diagonally symmetric, i.e. quadrants 100A and 100C were identical and quadrants 100B and 100D were identical. Each programmable logic quadrant 100A-100D included a programmable array 106, buried cells, output cells, input cells, feedback cells, and switch matrix cells. See for example FIGS. 7A, 7B, 8A, and 8B of U.S. Pat. No. 4,963,768.

This architecture provides significant flexibility, high speed performance, and better silicon die efficiency than prior art programmable logic device structures. While the above embodiment provides significant advantages over prior art devices, further enhancement in silicon die efficiency, speed, and flexibility are achieved by utilizing symmetric programmable logic blocks rather than only diagonally symmetric quadrants as in the above embodiment. In the embodiment described below, the product term flexibility is further enhanced.

In one embodiment, electrically programmable logic device 400 (FIG. 9) includes a plurality of identical programmable logic blocks 402, arranged in an array. Programmable logic blocks 402 are interconnected through programmable switch matrix 401. Programmable logic blocks 402 communicate with each other only through switch matrix 401. Moreover, programmable logic blocks 402 receive all input signals from switch matrix 401. Thus, programmable logic blocks 402 may be viewed as independent programmable logic devices on the same integrated circuit chip.

Each programmable logic block 402 may receive a first plurality of input signals from a plurality of input/output (I/O) pins 403 through switch matrix 401. The input signals, as explained more completely below, are passed through block 402 to switch matrix 401. Dedicated input pins 404 provide another plurality of input signals to switch matrix 401. The input signals processed by any logic block 402 are the signals received on input lines 426 from switch matrix 401. Each programmable logic block 402 may also provide a first plurality of output signals for I/O pins 403.

Each of programmable logic blocks 402 may include a PLA circuit, a PAL circuit, a programmable NAND.NAND circuit, or a programmable NOR.NOR circuit for example. In one embodiment, each programmable logic block 402 includes a programmable AND/OR logic array based PAL circuit. Each programmable logic block 402 has the same fixed number of input lines from switch matrix 401 which drive on the order of eighty product terms.

This segmented structure, like the other embodiments described above, retains the benefits of a traditional PAL circuit such as the wide input decoding, multiplexing and demultiplexing capability, without increasing the array proportionally to the number of input lines. Further, the array size and switch matrix 401 have been selected so that programmable logic device 400 of this invention achieves an optimum balance of functionality, silicon die size, and performance, in particular speed performance.

An important aspect of this invention is the fixed number of input lines to each programmable logic block 402 from switch matrix 401. As described more completely below, this feature maintains the speed performance of the device as the input/output capability is increased and this feature enhances the designer's ability to migrate a design to other devices in the family of programmable logic device 400.

Prior art devices typically provide to the programmable logic array one input line for each logic macrocell in the programmable logic block and one input line to the programmable logic array for each dedicated input pin. Each input line to the programmable logic array typically drives two lines within the array. Hence, in these prior art devices, as the number of physical pins increases the number of macrocells increases and consequently the number of input lines to the programmable logic array. As the number of input lines increases, the programmable logic array size increases. The larger array size results in poor speed performance and poor utilization of the array. Also, increasing the size of the programmable logic array limits migrating designs to other devices with enhanced input/output capability.

Another important aspect in one embodiment of this invention is the complete symmetry of programmable logic device 400. Each of the programmable logic blocks 402 in device 400 are identical. Moreover, programmable logic blocks 402 in programmable logic device 400 are preferably arranged symmetrically around switch matrix 401 (FIG. 9). The symmetry simplifies the development of the silicon die by the silicon chip designer and the design of a system using the PLD of this invention by the system designer. Also, without the inherent symmetry, the development of software tools for the PLD is more difficult.

Switch matrix 401 provides a means for selecting input signals for each programmable logic block 402. Switch matrix 402 can route signals from one block to another block, signals from the dedicated input pins to a block or blocks and a signal from a block back to that block. Signal transfer through this switch matrix is very rapid and signal path flexibility through the switch matrix for each programmable logic block provides numerous combinations of input signals to each programmable logic block of the device, as described more completely below. Also, switch matrix 401 provides a fixed, path independent, uniform, predictable and deterministic time delay for signals routed through switch matrix 401.

In one embodiment, switch matrix 401 is implemented using programmable multiplexers. As described more completely below, multiple configurations of switch matrix 401 are feasible using programmable multiplexers. The number of multiplexers and size of each multiplexer is a tradeoff between the size of the die, silicon utilization, and speed performance. A preferred embodiment is described below and in view of this discussion other embodiments will be apparent to those skilled in the art.

As illustrated in more detail in FIG. 10, each programmable logic block 402 contains a programmable logic array, for example a product-term array 410, a logic allocator 411, programmable logic macrocells 412, and I/O macrocells 4-3. Product-term array 410 generates the basic logic using signals provided only by switch matrix 401.

While programmable logic array 410 is described in terms of a programmable AND/OR array, the programmable AND/OR array is implemented in a preferred embodiment as a NOR.NOR array that is functionally equivalent to the programmable AND/OR array described herein. As discussed more completely below, product term array 410 may also be a programmable OR array/fixed AND array, a PLA (programmable AND array and a programmable OR array), a NOR.NOR array, or a NAND.NAND array, for example. Accordingly, the use of a programmable AND/OR logic array is illustrative only and is not intended to limit the scope of the invention.

Logic allocator 411 is programmable so that product terms from array 410 are distributed to logic macrocells 412 as required by the user of device 400. Logic macrocells 412 configure the signals from logic allocator 411 as explained more completely below. Each logic macrocell includes a programmable storage element.

The output signals from logic macrocells 412 are provided to I/O macrocells 413 and fedback to switch matrix 401 over lines 427. Each logic macrocell that may be used to generate an output signal is coupled to an I/O macrocell. I/O macrocells 413 selectively deliver the output signals from macrocells 413 to I/O pins 403. Alternatively, I/O macrocells 413 provide input signals from I/O pins 403 to switch matrix 401 over lines 428. If an I/O cell is used to configure an I/O pin as an input pin, the logic macrocell associated with that I/O cell can function as a buried logic macrocell. Hence, as explained more completely below, the architecture of programmable logic device 400 is designed for efficient use of all the resources within the device.

Each programmable logic block 402 additionally contains, in one embodiment, an asynchronous reset product term and an asynchronous preset product term. These product terms are used to initialize all flip-flops within programmable logic block 402. In addition, in one embodiment, each programmable logic block 402 contains two output enable product terms for every eight I/O macrocells in the block. In another embodiment, each programmable logic block 402 contains two output enable product terms for every six I/O macrocells in the block. In each programmable logic block 402, I/O macrocells 413 are divided into banks where each bank, in this embodiment, contains either eight or six I/O macrocells. Each bank of I/O macrocells 413 receives two of the output enable product terms.

Thus, each programmable logic block 402, in this embodiment, has a multiplicity of product terms in product term array 410 which provide control functions to all macrocells in block 402. In contrast, most prior art EPLDs had a plurality of control product terms associated with each macrocell. In most synchronous registered applications, the prior art plurality of control product terms were not completely utilized. Thus, prior art devices with a plurality of control product terms per macrocell were typically very inefficient. Consequently, the die size and the cost of the prior art devices were larger than required. In contrast, the control product terms of this invention provide functionality equivalent to that typically implemented with prior art devices while eliminating the inefficient use of resources within the device.

As described more completely below, programmable interconnections within each programmable logic block 402 are used to decouple product-term array 410 from switch matrix 401, macrocells 412, 413 and I/O pins 403. This decoupling provides greater flexibility than was available in the prior art programmable logic devices and allows device 400 to be efficiently and quickly configured for a user application. Another significant advantage of this architecture is that switch matrix 401 provides a fixed, path independent uniform predictable and deterministic time delay for all signals that are passed through switch matrix 401. Hence, in many circumstances, the performance of a design is design-independent and is known before the design is even begun.

In addition, switch matrix 401 allows optimized global connectivity and high silicon efficiency. In this embodiment, the delay time through switch matrix 401 for connecting one programmable logic block to another programmable logic block is in the range of about one to two nanoseconds. However, this delay time is technology dependent and a switch matrix implemented using a new advanced technology should have even less time delay. In contrast, prior art centralized programmable interconnect array based architectures had an interblock delay time in the range of from 13 to 16 nanoseconds. The high internal speed of switch matrix 401 of this invention allows a programmable logic block to communicate with other programmable logic blocks without the normal output buffer delays.

The decoupling of the internal resources within a programmable logic block 402 is in sharp contrast to the prior art programmable logic device families. Historically, two of the most popular synchronous programmable logic device families have been the industry standard low complexity 16R8/16V8 architecture programmable logic devices and the medium complexity 22V10 architecture programmable logic devices. Each of these device architectures includes a programmable AND-OR array.

In each of these three industry standard synchronous programmable logic devices, i.e., the 16R8, 16V8 and 22V10 devices, the AND-OR array is strongly coupled with the macrocells, i.e., the product terms associated with each of the macrocells belong to that particular macrocell only. The macrocells are also strongly coupled with the I/O pins. If the I/O pin is used as the input pin then the register associated with the I/O pin is lost. These devices do not provide the capability of operating the storage elements as buried registers. Also, a dedicated output enable product term for each of the I/O pins results in inefficient product term array utilization.

The major shortcomings of the existing synchronous programmable logic devices have been (i) complete coupling of macrocells with the AND-OR array and I/O pins, (ii) static allocation of product terms with macrocells, (iii) the absence of T-type flip-flops within the macrocells for building counters, (iv) the lack of flexible clock source selection, (v) the dedication of individual output enable product terms for each I/O pin; (vi) a limited number of I/O pins; and (vii) a limited number of macrocells.

Moreover, complete coupling of macrocells to the programmable array and the I/O pins with fixed, static allocation of product terms for logic and control function results in poor silicon efficiency and speed degradation. Also, migration of the architecture into high density structures becomes extremely difficult. In particular, prior art devices, which have increased numbers of I/O pins and macrocells, typically have poor speed performance and the architecture is not amenable to increased density because, as explained above, the product term array is further enlarged as the number of macrocells increases.

In contrast, programmable logic blocks 402 (FIG. 10) of this embodiment provide a simple high performance, yet flexible dense and scalable architecture. Programmable logic blocks 402 include the best features of the popular industry standard programmable logic devices as described above, such as architectural simplicity with a single programmable logic array and macrocell structures, along with decoupled elements and an optimized global connectivity with fixed high speed predictable delays. Programmable logic blocks 402 eliminate the poor silicon efficiency of the prior art devices.

In one embodiment, programmable logic device 400 of this invention is implemented with 0.8 micron double metal, electrically erasable CMOS technology. Further, for this technology, device 400 has about a 15 nanosecond worst case pin-to-pin signal propagation delay time with a 50 Mhz external system clock. However, it is anticipated that with new technology, the architecture of this invention will have even faster speed performance, e.g., a 12 nanosecond propagation time delay with external system clock in the range of 66 to 80 MHz and possibly even faster. Moreover, according to the principles of this invention, the logic macrocells, both output and buried, are decoupled from the product term array by the switch matrix and the logic allocator. As the number of macrocells is increased, the product term array is not proportionally affected. Therefore, unlike the prior art devices, the product term array of this invention does not degrade speed performance as the density of macrocells is increased.

In fact, as the logic macrocell density is increased, the pin-to-pin signal propagation delay time remains about constant because the switch matrix provides a fixed known delay, and the product term array size is maintained. Thus, a design implemented with one device of this invention is easily migrated to a device having more macrocell capability. As explained more completely below, with this architecture there is no longer a need to trade device speed for macrocell density.

Symmetric programmable logic device 400 with programmable switch interconnect matrix 401, in this embodiment, is further subdivided into two families. A first family 400A (Table 1) includes 44, 68, and 84 pin devices with 32, 48 and 64 logic macrocells respectively. This family, with a high pin-to-logic ratio, is targeted to address I/O intensive applications.

Conversely, a second family 400B (Table 1), with a high logic-to-pin ratio, is targeted to address logic intensive applications. The second family offers twice the logic capability of the first family in the same package. The use of two families provides a convenient way for migrating designs up or down with little difficulty. The I/O and logic intensive nature of the families offers system designers broader options, allowing them to suit their designs to appropriate devices.

The features for several embodiments of each family are given in Table 1.

                  TABLE 1                                                          ______________________________________                                                   Logic                                                                          Macro-   I/O       Max   Max    Max                                  Pins      cells    Macrocells                                                                               Inputs                                                                               Outputs                                                                               F/Fs                                 ______________________________________                                         Family 1                                                                       110    44     32       32      38    32     32                                 120    68     48       48      56    48     48                                 130    84     64       64      70    64     64                                 Family 2                                                                       210    44     64       32      38    32     64                                 220    68     96       48      56    48     96                                 230    84     128      64      70    64     128                                ______________________________________                                    

The column "Pins" in Table 1 is the total number of pins for the package containing programmable logic device 400. The columns "Max Inputs" and "Max Outputs" correspond to the total number of pins available for input signals and output signals, respectively. In this embodiment, each of the devices has either six or eight dedicated input pins. Further, as explained below, in PLDs 110 and 210, two of the dedicated input pins may function either as clock sources or input sources, while in PLDs 120, 130, 220, and 230, four of the dedicated input pins may function either as clock sources or input sources. The column "Max F/Fs" represents the maximum number of flip-flops in the PLD and as explained more completely below, in this embodiment each logic macrocell in both families includes one programmable storage element.

FIGS. 11, 12A, 12B, 13A and 13B are block diagrams illustrating the first family 400A of programmable logic devices 110, 120 and 130, respectively, according to the principles of this invention. (In the figures, a component with "A1" in the reference numeral is a component in device 110, with "A2" in the reference numeral is a component in device 120, and with "A3" in the reference numeral is a component in device 130.)

FIG. 11 illustrates 44 pin device 110 which has 32 I/O pins 403A1-1 to 403A1-32 and six dedicated direct input pins 404A1-1 to 404A1-6. As previously described, each of programmable logic blocks 402A1-1, 402A1-2 is identical and each includes a programmable product term array, preferably a 44×70 product term array 410A1-1, 410A1-2, a programmable logic allocator 411A1-1, 411A1-2, 16 programmable logic macrocells 412A1-1, 412A1-2, and 16 programmable I/O macrocells 413A1-1, 413A1-2. Notice that in FIGS. 11, 12A, 12B, 13A and 13B, product term array 410A and logic allocator 411A have been combined and are represented by a single box 410A-411A.

In the figures, a line with a slash through the line and then a number N is used to indicate that the line represents N lines. Hence, switch matrix 401A1 provides twenty-two input signals to product term array 410A1 over twenty-two input lines 426A1-1. Similarly, logic macrocells 412A1-1 provide feedback signals to switch matrix 401A1 over sixteen lines 427A1-1 and I/O macrocells 413A1-1 provide I/O pin feedback signals to switch matrix 401A1 over sixteen lines 428A1-1. The other block 402A-2 is similarly configured.

In FIG. 11, two dedicated input pins 404A1-3, 404A1-6 are either a dedicated input pin, a dedicated clock pin, or a clock/input pin. Pins 404A1-3, 404A1-6 are coupled to switch matrix 401A1 and to logic macrocells 412A1.

Hereinafter for all PLDs of this invention, any pin that provides a clock signal may also provide a latch enable signal. The actual signal on the pin is determined by the configuration of the programmable storage element in the logic macrocell, as explained more completely below. Therefore, any reference, such as "CLK0", is actually "CLK0/LE0", but in most cases only the label "CLK0" is shown for simplicity. Herein, "/" is used to indicate a multiple function capability. The labeling such as "CLK0" is not intended to limit the operation of the dedicated input pins. In view of this disclosure, the operative signal required on each dedicated input pin for proper functioning of the programmable storage elements in the logic macrocells will be apparent to those skilled in the art.

FIG. 12A and 12B are similar to FIG. 11 but in this embodiment, programmable logic device 120 includes four identical programmable logic blocks 402A2 and has eight dedicated input pins, four of which may be used as either dedicated clock signal input pins, dedicated direct input pins, or dedicated clock/input pins.

Specifically, FIGS. 12A and 12B illustrates 68 pin device 120 which has 48 I/O pins 403A2-1 to 403A2-48 and eight dedicated direct input pins 404A2-1 to 404A2-8. As previously described, each of the programmable logic blocks 402A2-1 to 402A2-4 is identical and each includes a programmable product term array, preferably a 52×54 product term array 410A2-1 oo 410A2-4, a programmable logic allocator 411A2-1 to 411A2-4, 12 programmable logic macrocells 412A2-1 to 412A2-4, and 12 programmable I/O macrocells 413A2-1 to 413A2-4.

A second embodiment 401A2 of switch matrix 401 provides twenty-six input signals to product term array 410A2-1 over twenty-six input lines 426A2-1. Similarly, logic macrocells 412A2-1 provide feedback signals to switch matrix 401A2 over twelve lines 427A2-1 and I/O macrocells 413A2-1 provide I/O pin feedback signals to switch matrix 401A2 over twelve lines 428A2-1. The other blocks in PLD 120 are similarly configured. In FIGS. 12A and 12B, four dedicated input pins 404A2-3, 404A2-4, 404A2-7 and 404A2-8 are used either as a dedicated input pin, a dedicated clock pin, or a clock/input pin. Pins 404A2-3, 404A2-4, 404A2-7 and 404A2-8 are coupled to switch matrix 401A2 and to logic macrocells 412A2.

FIGS. 13A and 13B are similar to FIGS. 12A and 12B, but in this embodiment, programmable logic device 130 includes four identical programmable logic blocks 402A3 and has six dedicated input pins, four of which may be used as dedicated clock signal input pins, dedicated direct input pins, or clock/input pins.

Specifically, FIGS. 13A and 13B illustrate 84 pin device 130 which has 64 I/O pins 403A3-1 to 403A3-64 and six dedicated direct input pins 404A3-1 to 404A3-6. As previously described, each of the programmable logic blocks 402A3-1 to 402A3-4 is identical and each includes a programmable product term array, preferably a 52×70 product term array 410A3-1 to 410A3-4, a programmable logic allocator 411A3-1 to 411A3-4, 16 programmable logic macrocells 412A3-1 to 412A3-4, and 16 programmable I/O macrocells 413A3-1 to 413A3-4.

A third embodiment 401A3 of switch matrix 401 provides twenty-six input signals to product term array 410A3-1 over twenty-six input lines 426A3-1. Similarly, logic macrocells 412A3-1 provide feedback signals to switch matrix 401A3 over sixteen lines 427A3-1 and I/O macrocells 413A3-1 provide I/O pin feedback signals to switch matrix 401A3 over sixteen lines 428A3-1. Each of the other programmable logic blocks is similarly configured.

Four dedicated input pins 404A3-2, 404A3-3, 404A3-5 and 404A3-6 are either a dedicated input pin, a dedicated clock pin, or a clock/input pin. Pins 404A3-2, 404A3-3, 404A3-5 and 404A3-6 are coupled to switch matrix 401A3 and to logic macrocells 412A3.

FIGS. 14A through 16D are block diagrams of PLDs 210, 220, and 230 respectively of second family 400B of programmable logic devices according to the principles of this invention. As previously described, this family 400B of logic devices has a higher logic to pin ratio than the first family 400A. Thus, in one embodiment, each programmable logic block 402B has only eight I/O pins 403B. In another embodiment, each programmable logic block 402B has only six I/O pins 403B. Product term array 410B, logic allocator 411B and logic macrocells 412B in programmable logic block 402B are similar to the corresponding components in programmable logic block 402A. However, as explained more completely below, logic macrocells 412B include output logic macrocells 412BA and buried logic macrocells 412BB.

FIGS. 14A and 14B illustrate 44 pin device 210 which has 32 I/O pins 403B1-1 to 403B1-32 and six dedicated direct input pins 404B1-1 to 404B1-6. As previously described, each of programmable logic blocks 402B1-1 to 402B1-4 is identical and each includes a programmable product term array, preferably a 44×68 product term array 410B1-1 to 410B1-4, a programmable logic allocator 411B1-1 to 411B1-4, 16 programmable logic macrocells divided into eight programmable logic macrocells 412BA1-i-1 to 412BA1-i-8 and eight buried programmable logic macrocells 412BB1-i-1 to 412BB1-i-8 where i represents the programmable logic block. Notice that as in the previous figures, product term array 410B and logic allocator 411B have been combined and are represented by a single box 410B-411B.

A fourth embodiment 401B1 of switch matrix 401 provides 22 input signals to product term array 410B1-1 over 22 input lines 426B1-1. Similarly, programmable logic macrocells 412BA1-1 provide eight feedback signals to switch matrix 401B1 over eight lines in lines 427B1-1 and buried programmable logic macrocells 412BB1-1 provide another eight feedback signals to switch matrix 401B1 over another eight lines in lines 427B1-1. I/O macrocells 413B1-1 provide I/O pin feedback signals to switch matrix 401B1 over eight lines 428B1-1. The other blocks in device 210 are similarly configured. In FIGS. 14A and 14B, two dedicated input pins 404B1-3, 404B1-6 are either a dedicated input pin, a dedicated clock pin, or a clock/input pin. Pins 404B1-3, 404B1-6 are coupled to switch matrix 401B1 and to logic macrocells 412BA and 412BB.

FIGS. 15A to 15D illustrate 68 pin device 220 which has 48 I/O pins 403B2-1 to 403B2-48 and eight dedicated direct input pins 403B2-1 to 403B2-8. As previously described, each of programmable logic blocks 402B2-1 to 402B2-8 is identical and each includes a programmable product term array, preferably a 52×52 product term array, 410B2-1 to 410B2-8, a programmable logic allocator 411B2-1 to 411B2-8, 12 programmable logic macrocells divided into a first group of six programmable logic macrocells 412BA2-i-1 to 412BA2-i-6 and a second group of six buried programmable logic macrocells 412BB2-i-1 to 412BB2-i-6, where i represents the programmable logic block.

A fifth embodiment 401B2 of switch matrix 401 provides 26 input signals to product term array 410B2-1 over 26 input lines 426B2-1. Similarly, programmable logic macrocells 412BA2-1 provide six feedback signals to switch matrix 401B2 over six lines in lines 427B2-1 and six buried programmable logic macrocells 412BB2-1 provide another six feedback signals to switch matrix 401B2 over another six lines in lines 427B2-1. I/O macrocells 413B2-1 provide I/O pin feedback signals to switch matrix 401B2 over six lines 428B2-1. The other blocks in device 220 are similarly configured. In FIGS. 15A to 15D, four dedicated input pins 404B2-3, 404B2-4, 404B2-7 and 404B2-8 are either a dedicated input pin, a dedicated clock pin, or a clock/input pin. Pins 404B2-3, 404B2-4, 404B2-7 and 404B2-8 are coupled to switch matrix 401B2 and to logic macrocells 412BA and 412BB.

FIGS. 16A to 16D illustrate 84 pin device 230 which has 64 I/O pins 403B3-1 to 403B3-64 and six dedicated direct input pins 403B3-1 to 403B3-6. As previously described, each of programmable logic blocks 402B3-1 to 402B3-8 are identical and each includes a programmable product term array, preferably a 52×68 product term array, 410B3-1 to 410B3-8, a programmable logic allocator 411B3-1 to 411B3-8, 16 programmable logic macrocells divided into a first group of eight programmable logic macrocells 412BA3-i-1 to 412BA3-i-8 and a second group of eight buried programmable logic macrocells 412BB3-i-1 to 412BB3-i-8.

A sixth embodiment 401B3 of switch matrix 401 provides 26 input signals to product term array 410B3-1 over 26 input lines 426B3-1. Similarly, eight programmable logic macrocells 412BA3-1 provide eight feedback signals to switch matrix 401B3 over eight lines in lines 427B3-1 and eight buried programmable logic macrocells 412BB3-1 provide another eight feedback signals to switch matrix 401C over another eight lines in lines 427B3-1. I/O macrocells 413B3-1 provide I/O pin feedback signals to switch matrix 401B3 over eight lines 428B3-1. The other blocks in device 230 are similarly configured. In FIGS. 16A to 16D, four dedicated input pins 404B3-2, 404B3-3, 404B3-5 and 404B3-6 are either a dedicated input pin, a dedicated clock pin, or a clock/input pin. Pins 404B3-2, 404B3-3, 404B3-5, and 404B3-6 are coupled to switch matrix 401B3 and to logic macrocells 412BA and 412BB. Extension of the principles of second family 400B of programmable logic devices 400 to other logic macrocells to pin ratios, e.g. 3:1 or 4:1, will be apparent to those skilled in the art in view of this disclosure.

A programmable logic block 402A1-i of PLD 110 of this invention is shown in more detail in FIGS. 17A to 17D, where i=1, 2, 3 or 4. In particular, the interconnection of switch matrix 401A1, 44×70 product term array 410A1-i, logic allocator 411A1-i, a column of sixteen logic macrocells 412A1-i, a column of sixteen I/O macrocells 413A1-i and a column of sixteen I/O pins 403A1-i are illustrated. Product term array 410A1-i includes a 44 by 70 programmable AND logic array. Sixty-four of the product term lines are provided to logic allocator 411A1-i. In addition, product term array 410A1-i in this embodiment has six additional product term lines 410A1-i-65 through 410A1-i-70.

In FIGS. 17A to 17D, a single line is shown connecting logic allocator 411A1-i to each logic macrocell 412A1-i-n (n=1, . . . , 16). However, as explained more completely below, the line between logic allocator 411A1-i and each macrocell 412Al-i-n represents a multiplicity of lines, e.g. 3 to 4 lines.

I/O macrocells 413A1-i, in this embodiment, are divided into two banks. The first bank of I/O macrocells 413A1-i is defined by I/O macrocells 413A1-i-1 to 413A1-i-8 that receive the signals on output enable product term lines 410A1-i-65 and 410A1-i-66. Similarly, the second bank of I/O macrocells 413A1-i is defined by I/O macrocells 413A1-i-9 to 413A1-i-16 that receive signals on output enable product term lines 410A1-i-69 and 410A1-i-70. The signals on lines CLK0, CLK1 from dedicated input pins 404A1-3, 404A1-6 (FIG. 12A) are provided to each logic macrocell 412A1-i (FIGS. 17B and 17D). Similarly, the product term on asynchronous reset line 410A1-i-67 and the product term on asynchronous preset line 410A1-i-68 are provided to each of logic macrocells 412A1-i.

Product term array 410A2 (FIGS. 12A and 12B) is a 52×54 programmable AND logic array. The 54 product terms include 48 logic product terms and six control product terms. Similarly, product term array 410A3 (FIGS. 13A and 13B) is a 52×70 programmable AND logic array with 64 logic product terms and six control product terms. Both arrays 410A2 and 410A3 are configured substantially as illustrated in FIGS. 17A to 17D when the different number of input lines from the switch matrix, the number of logic macrocells, and the two additional clock sources are considered. In addition, as described more completely below, the logic allocator and logic macrocells in PLDs 120, 130 provide even greater flexibility than that provided in PLD 110.

Extensive studies of the popular prior art PAL devices' usage pattern showed that for a given technology, the product term array degrades speed performance as the array becomes larger. As a result, each product term array 410A in this embodiment has either twenty-two or twenty-six input lines from switch matrix 401A. Each input line from switch matrix 401A is connected to a driver that provides both the signal on the input line and the complement of the signal on the input line to the product term array which in turn generates all the logic and control product terms for the programmable logic block.

The product term array size of this invention is sized between the product term arrays in the 16V8 architecture and the 22V10 architecture described above. Thus, the product term array is optimized to have the performance and cost structure of the 16V8 architecture with higher silicon efficiency than either the 16V8 or 22V10 architecture. In fact, the product term array of this invention has the equivalent logic functionality of the 22V16 or 26V16 PAL-like architecture, but this functionality is provided in a programmable logic device that is approximately one-half the size of the 22V10 block.

Programmable logic block 402B1-i for PLD 210 in second family 400B of programmable logic devices of this invention is shown in more detail in FIGS. 18A to 18D. In particular, the interconnection of switch matrix 401B1, product term array 410B1-i, logic allocator 411B1-i, a column of sixteen logic macrocells 412B1-i, which has eight output logic macrocells 412BA1-i and eight buried logic macrocells 412BB1-i, a column of eight I/O macrocells 413B1-i and a column of eight I/O pins 403B1-i are illustrated. Product term array 410B1-i includes a 44×68 programmable AND logic array. Sixty-four of the product term lines are provided to logic allocator 411B1-i. In addition, product term array 410B1-i in this embodiment has four additional product term lines 410B1-i-65 through 410B1-i-68.

Product term array 410B2 (FIGS. 15A to 15D) is a 52×52 programmable AND logic array. The 52 product terms include 48 logic product terms and four control product terms. Similarly, product term array 410B3 (FIGS. 16A to 16D) is a 52×68 programmable AND logic array with 64 logic product terms and four control product terms. Both arrays 410B2 and 410B3 are configured substantially the same way as illustrated in FIGS. 18A to 18D when the different number of input lines from the switch matrix, the number of logic macrocells, and the two additional clock sources are considered.

I/O macrocells 413B1-i, in this embodiment, receive the signals on output enable product term lines 410B1-i-65 and 410B1-i-66. The signals on lines CLK0, CLK1 from dedicated input pins 404B1-3, 404B1-6 (FIGS. 14A and 14B) are provided to each output logic macrocell 412BA1-i and buried logic macrocell 412BB1-i (FIGS. 18B and 18D). Similarly, the product term on asynchronous reset line 410B1-i-67 and the product term on asynchronous preset line 410B1-i-68 are provided to each output logic macrocell 412BA1-i and buried logic macrocell 412BB1-i.

Each I/O pin is connected to a buried logic macrocell so that, as explained more completely below, when the I/O pin is configured as an input pin, the input signal is supplied to both the buried logic macrocell and switch matrix 401B. Thus, the input signal may be either processed by the buried logic macrocell, i.e., may be a registered input signal, and then provided to switch matrix 401B or provided directly to switch matrix 401B as a simple combinatorial input signal.

Switch matrix 401B is coupled to programmable product term array 410B by either twenty-two or twenty-six input lines. As described above for switch matrix 401A, each input line from switch matrix 401B is connected to a driver that generates the signal on the input line and the complement of the signal on the input line.

Logic allocator 411 (FIG. 10) of this invention includes a multiplicity of router elements wherein each router element steers the sum of a selected number of sum of product terms from product term array 410 to a selected macrocell. The number of product terms per router element may be selected in numerous ways. In this embodiment, the selected number of product terms is four and there is one router element for each logic macrocell 412.

Hence, as described above, if a programmable logic block has sixteen logic macrocells, the product term array provides sixty-four product terms to logic allocator 411. Similarly, in the embodiment which has 12 logic macrocells per programmable logic block, the product term array provides forty-eight product terms to the logic allocator. The configuration of router elements described herein is illustrative only of a plurality of router elements with each router element steering a fixed number of product terms to a selected macrocell and is not intended to limit the invention to the specific configuration described.

In first family 400A of logic devices 400, logic allocator 411A in PLDs 110, 120 and 130 includes either sixteen or twelve router elements 520A (FIG. 19). Each router element 520A includes OR gate 521A, which is driven by signals from four product term lines in product term array 410A, and a programmable one-to-three demultiplexer 522A which has a single input terminal and three output terminals. Architectural configuration cells 523A, 524A are used to form a connection between the input terminal and only one of the output terminals, as explained more completely below. Cells 523A, 524A provide an output select signal to demultiplexer 522A so that the signal on the input line is passed therethrough to the selected output line. In this embodiment, OR gate 521A is included within router element 520A, but alternatively the OR gate could be included with the AND array so that a programmable AND-OR array generated signals for logic allocator 411A.

In PLD 11O, two router elements 520A1-1, 520A1-9 (FIG. 20A) of logic allocator 411A1 may provide a signal to only two macrocells, e.g. router element 520A1-1 drives either logic macrocell 412A1-i-1 or logic macrocell 412A1-i-2 (FIG. 17B) and router element 520A1-9 drives either logic macrocell 412Al-i-9 or logic macrocell 412A1-i-10 (FIG. 17D). Similarly, router elements 520A1-8, 520A1-16 (FIG. 20C) in logic allocator 411A1 may provide a signal to only two macrocells. Element 520A1-16 drives either logic macrocell 412Al-i-15 or logic macrocell 412Al-i-16 (FIG. 17D) and element 520A1-8 drives either logic macrocell 412A1-i-7 or logic macrocell 412A1-i-8 (FIG. 17B). Each of the other twelve router elements 520A1-i-n (FIG. 20B) in logic allocator 411A1 may provide a signal to the macrocell 412A1-i-(n-1) or to macrocell 412A1-i-n, or to macrocell 412A1-i-(n+1), where n=2, 3, . . . , 7, 10, . . . , 15.

Thus, in this embodiment, logic macrocells 412A1-i-2 through 412A1-i-7 and 412A1-i-9 through 412A1-i-15 may receive up to a maximum of a sum of twelve product terms while logic macrocells 412A1-i-1 and 412A1-i-16 may receive up to a maximum of a sum of only eight product terms. Logic macrocells 412Al-i-1, 412Al-i-8, 412A1-i-9 and 412A1-i-16 receive only up to a sum of eight product terms because complete wraparound at the end of programmable logic block 402A1, e.g., providing a line from demultiplexer 522A1-16 to logic macrocell 412A1-i-1, is not supported. In one embodiment, complete wraparound is estimated to cause a degradation in speed performance of about one to two nanoseconds for signal propagation from an input pin through programmable logic device 110 to an output pin.

The operation of logic allocator 411A1 is illustrated in FIG. 21. Boxes L1 through L16 on the left-hand side of the figure, each of which contains the numeral "4", represent the product term clumps, each of which has four product terms, in product term array 410A1. On the right-hand side of FIG. 21 are 16 boxes R1 through R16 which represent logic macrocells 412A1-i-1 to 412A1-i-16 respectively. The number within boxes R1 to R16 is the maximum number of product terms that logic allocator 411A1 can route to that logic macrocell. The numbers within logic allocator 411A1 represent the product terms as numbered on the left-hand side of the figure. Accordingly, FIG. 21 clearly illustrates the product term steering capability of logic allocator 411A1 of this invention.

It is important to note that no product term resources are permanently allocated to a specific macrocell by logic allocator 411A1. Accordingly, if an I/O pin that is coupled to a macrocell, for example the macrocell labeled R8 in FIG. 21, is used as an input pin and the buried register capability of macrocell R8 is not needed, the product terms from cells L7 and L8 in product term array may be utilized by macrocell R7. Thus, there are no wasted product terms associated with macrocell L8, when the macrocell is not utilized.

The signal passed from the output terminal of OR gate 521A (FIGS. 19, 20A, 20B and 20C) is provided to the input terminal of demultiplexer 522A and the output terminal of demultiplexer 522A that receives the input signal is determined by the configuration of architectural cells 523A and 524A. The possible values of the architectural cells 523A1 and 524A1 (FIGS. 20A to 20C) are shown in Table 2 along with the logic macrocell that receives the sum of product terms when the architectural cells have these values. The numbers n, n-1 and n+1 in Table 2 are as defined in FIG. 20B. The configuration of architectural cells in Table 2 as well as the other Tables herein is illustrative only and is not intended to limit the invention to the specific configuration given.

                  TABLE 2                                                          ______________________________________                                         Product Term Steering                                                          Architectural                                                                             Architectural                                                                               Output Signal Supplied                                 Cell 523A  Cell 524A    to Logic Macrocell                                     ______________________________________                                         0          0            reserved                                               0          1            412A1-i-(n - 1)                                        1          0            412A1-i-n                                              1          1            412A1-i-(n + 1)                                        ______________________________________                                    

In Table 2, a zero corresponds to a logic zero and is equivalent to a programmed state and a one corresponds to a logic one and is equivalent to an unprogrammed or erased state. Of course, as is known to those skilled in the art, alternative definitions of the programmed and unprogrammed states may be used with the principles of this invention to define alternative embodiments of the family of high performance, high density, programmable logic structures of this invention. The programming for router elements 520A1-1, 520A1-8, 520A1-9, and 520A1-16 is also given by Table 2, where n=1, 8, 9 and 16 respectively where (i) the logic macrocell 412A1-i-(n-1) is reserved for router elements 520A1-1 and 520A1-9; and (ii) the logic macrocell 412A1-i-(n+1) is reserved for router elements 520A1-8 and 520A1-16.

PLDs 120 and 130 include in logic allocators 411A2 and 411A3 respectively router elements 520A (FIG. 19). The configuration of the router elements within these logic allocators is substantially similar to that described for logic allocator 411A1 except for the router elements corresponding to router elements 520A1-8 and 520A1-9. Router elements 520A1-8 and 520A1-9 effectively divided logic allocator 411A1 in PLD 110 into two banks, but in PLDs 120 and 130 all of the router elements except the first and the last router element can steer the sum-of-product terms to three different logic macrocells. The operation of logic allocator 411A2 is illustrated in FIG. 22. Boxes L1 through L12 and boxes R1 through R12 and the numbers within the logic allocator are defined in a manner similar to those in FIG. 21. Similarly, the operation of logic allocator 411A3 is illustrated in FIG. 23. Thus, FIGS. 21 to 23 clearly show that the first and last logic macrocell in each programmable logic block receive only up to a sum of eight product terms because complete wraparound at the end of the programmable logic block is not supported. All other programmable logic macrocells in PLDs 120 and 130 receive up to a sum of twelve product terms.

In the second family 400B of logic devices, logic allocator 411B includes either sixteen or twelve router elements 520B (FIG. 24). Each router element 520B includes OR gate 521B, which is driven by signals from four product term lines in product term array 410B, and a programmable one-to-four demultiplexer 522B which has a single input terminal and four output terminals. Architectural configuration cells 523B, 524B are used to form a connection between the input terminal and only one of the output terminals, as explained more completely below.

First router element 520B1-1 (FIG. 25A) of logic allocator 411B1 may provide a signal to either output logic macrocell 412BA1-i-1 (FIG. 18B), or buried logic macrocell 412BB1-i-1. Second router element 520B1-2 (FIG. 25B) may provide a signal to either output logic macrocell 412BA1-i-1 (FIG. 18B), buried logic macrocell 412BB1-i-1 or output logic macrocell 412BA1-i-2. Last router element 520B1-16 (FIG. 25D) in logic allocator 411B1 may provide a signal to buried logic macrocell 412BB1-i-7 (FIG. 18D), output logic macrocell 412BA1-i-8, or buried logic macrocell 412BB1-i-8.

Each of the other thirteen router elements 520B1-n (FIG. 25C) in logic allocator 411B1 may provide a signal to one of four logic macrocells. The four output lines from demultiplexer 522B1-n are given as lines to macrocells 412B1-i-(n-2), 412B1-i-(n-1), 412B1-i-(n), and 412B1-i-(n+1) where n=3,4, . . . , 15. Here, n represents the position of router element 520B1-n in the column of router elements within logic allocator 411B1-i. To locate the output logic macrocells and buried logic macrocells 412B1-i-(n-2), . . . , 412B1-i-(n+1) to which the output lines n-2, . . . , n+1 from programmable demultiplexer 522B1-n are connected, column 412B1-i of output logic macrocells 412BA1-i and buried logic macrocells 412BB1-i (FIGS. 18B and 18D) are numbered consecutively from one to sixteen where output logic macrocell 412BA1-i-1 is one and buried logic macrocell 412BB1-i-8 is sixteen, i.e., n=1 . . . 16. Line n is then connected to the nth logic macrocell in column 412B1-i.

For example, consider n=6, i.e., router element 520B1-6. The sixth macrocell in column 412B1-i (FIG. 18B) is output logic macrocell 412BB1-i-3 Thus, line n from router element 520B1-6 is connected to output logic macrocell 412BB1-i-3. Line n-1 is connected to buried logic macrocell 412BA1-i-3 and line n-2 is connected to output logic macrocell 412BB1-i-2. Line n+1 is connected to buried logic macrocell 412BA1-i-4.

Thus, in this embodiment, logic macrocells 412B1-i-2 through 412B1-i-14 may receive up to a maximum of a sum of sixteen product terms while logic macrocells 412B1-i-1 and 412B1-i-15 may receive up to a maximum of a sum of twelve product terms. Macrocell 412B1-i-16 may receive only up to a sum of eight product terms. Again, complete wraparound at the end of programmable logic block 402B is not supported.

The operation of logic allocator 411B1 is illustrated in FIG. 26. Boxes L1 through L16 on the left-hand side of the figure, each of which contains the numeral "4", represent the product term clumps, each of which has four product terms, in product term array 410B1. On the right-hand side of FIG. 26 are 16 boxes R1 through R16 where boxes R1, R3, . . . , R15 represent output logic macrocells and boxes R2, R4, . . . , R16 represent buried logic macrocells. The number within boxes R1 to R16 is the maximum number of product terms that logic allocator 411B1 can route to that logic macrocell. The numbers within logic allocator 411B1 represent the product terms as numbered on the left-hand side of the figure. Accordingly, FIG. 26 clearly illustrates the product term steering capability of logic allocator 411B1 of this invention.

It is important to note that no product term resources are permanently allocated to a specific macrocell by logic allocator 411B1. Thus, in this embodiment, as previously described for logic allocator 411A, there are no wasted product terms associated with a macrocell when the macrocell is not utilized.

The signal passed from the output terminal OR gate 521B1 is provided to the input terminal of demultiplexer 522B1 and the output terminal that receives the input signal is determined by the configuration of architectural cells 523B1 and 524B1. The possible values of the architectural cells 523B1 and 524B1 are shown in Table 3 and the numbers n, n-1, n-2, and n+1 are as defined in FIG. 25C. Again, the architectural cell values in Table 3 are illustrative only, as described above for Table 2, and are not intended to limit the invention to the particular values shown.

                  TABLE 3                                                          ______________________________________                                         Product Term Steering                                                          Architectural                                                                             Architectural                                                                               Output Signal Supplied                                 Cell 523B  Cell 524B    to Logic Macrocell                                     ______________________________________                                         0          0            (n - 2)                                                0          1            (n - 1)                                                1          0            n                                                      1          1            (n + 1)                                                ______________________________________                                    

In Table 3, a zero corresponds to a logical zero and is equivalent to a programmed state and a one corresponds to a logical one and is equivalent to an unprogrammed or erased state. The programming for cells 520B1-1, 520B1-2 and 520B1-16 is also given by Table 3 where n=1, 2 and 16 respectively.

PLDs 220 and 230 include in logic allocators 411B2 and 411B3 respectively router elements 520B (FIG. 24). The configuration of the router elements within these logic allocators is substantially similar to that described for logic allocator 411B1. The operation of logic allocator 411B2 is illustrated in FIG. 27. Boxes L0 through L11 and boxes R0 through R11 and the numbers within the logic allocator are defined in a manner similar to those in FIG. 26. Similarly, the operation of logic allocator 411B3 is illustrated in FIG. 28.

Thus, according to the principles of this invention, the numbers of sums of logical product terms for each macrocell 412 in programmable logic block 402 are variable and may range from a one sum of four product terms to four sums of four product terms, i.e., sixteen product terms, for each logic macrocell. Unlike most of the conventional industry standard programmable logic devices where product terms are preassigned and fixed with each macrocell either in an equal fixed distribution pattern, such as in the 16R8/16V8 architecture, or in a variable but fixed distribution pattern, such as the 22V10 architecture, according to the principles of this invention the product term resources are allocated to a specific macrocell as needed. This flexibility in allocation of product terms to macrocells results in significant increased utilization of the programmable AND array capability. Further, logic device 400 offers higher speed and lower cost over prior art equivalent high density devices.

One of the main reasons associated with the prior art low density PAL structures' silicon inefficiency was fixed product term allocation for each macrocell. Most of the synchronous PAL devices have a fixed overhead of seven or more logic product terms and less than one or two control product terms for each output pin. Although fixed allocation of product terms allows flexibility in having product terms available when needed, the product terms are wasted if the application for which the device is used requires less than the fixed allocated resources. The fixed allocation of product terms to macrocells along with fixed coupling of the macrocells to the I/O pins or I/O cells, as explained previously, results in significant silicon inefficiency and difficulty in migrating the architecture to higher densities.

Extensive studies of the most popular PAL device usage patterns have shown that a device with four to sixteen product terms per macrocell that contains either a D- or T-type flip-flop would address 90-95% of the high density synchronous programmable logic application needs. Any fixed allocation of product terms per macrocell, even two to three product terms per macrocell, may be wasteful. Thus, programmable logic device 400 has overcome these limitations by having no fixed allocation of product terms per logic macrocell, but yet device 400 through logic allocator 411 has four to sixteen product terms programmably available for each logic macrocell 412.

Also, we have discovered that 85-95% of synchronous logic applications of PAL device structures do not require individual control product terms, such as RESET, PRESET, output enable or clock, for each logic macrocell. Hence, prior art devices with a plurality of control product terms for each macrocell are not silicon efficient when used for synchronous applications because the majority of the control product terms are wasted. Further, as described above, for maximum silicon efficiency, the logic macrocells must be decoupled from both the product term array and the I/O pins.

However, simply decoupling the logic macrocells from the I/O pins is not sufficient for maximum silicon efficiency. While the decoupling of the logic macrocells from the I/O pins restores the usage of a logic macrocell as a buried register, such decoupling does not address the scalability problem. The more important problem is decoupling the product term array from the macrocells so that as the number of macrocells is increased, the product term array size remains constant or nearly constant, i.e. changes by about one to five input lines.

Logic allocator 411 allocates, as described above, product term resources in a variable distribution among all macrocells 412 in a programmable logic block 402. Thus, logic allocator 411 essentially decouples unused macrocells 412 from product term array 410 and allocates up to twelve to sixteen product terms per used logic macrocell 412 with minimal speed penalty, i.e., the pin to pin signal delay time, which includes the signal delay time of logic allocator 411, is smaller than equivalent density prior art devices.

Logic allocator 411 contrasts sharply with the expander array concept of second generation EPLDs family. More particularly to solve the fixed allocation product term inefficiency problem, some of the second generation mid-density EPLDs opted for the concept of an expander product term array. The expander array concept, which is a variation of folded NANDs array concept, is one attempt to solve the fundamental problem of a fixed overhead of at least seven to eight product terms per output pin. The expander product term array is a collection of unallocated product terms that are available for expanding logic capability of the programmable logic device.

However, since the expander array overhead is an addition to the fixed overhead of eight product terms per macrocell (three to four logic product terms plus four control product terms), this approach appears to degrade the product term overhead problems rather than solve the problems. Further, the expander array introduces a significant speed delay because the time for a signal to traverse the array was about 13-16 nanoseconds for logic requiring more than three product terms.

Thus, the expander array concept not only imposes a significant performance penalty on logic intensive applications of more than three product terms, but also the concept imposes a significant cost penalty in the fixed overhead associated with the expander array and consequently larger die size for less logic intensive functions. Hence, unlike the expander array, logic allocator 411 of this invention not only decouples product term array 410 from logic macrocells 412 but also results in elimination of the large speed degradation for logic intensive applications while providing silicon die efficiency. Specifically, fixed resources are not wasted upon configuration of device 400 for a specific application.

Each logic macrocell 412A1 of this invention in PLD 110 is identical so that logical output macrocell 412A1 (FIG. 29A) is representative of any logical macrocell 412A1 in this embodiment. In logical macrocell 412A1, a plurality of logic terms from logic allocator 411A1 are supplied on the n input lines to OR gate 500. The output line of OR gate 500 is connected to a first input terminal of a two-to-one programmable output path selection multiplexer 505 and to the input terminal of a rising-edge triggered programmable D or T type flip-flop 503 with asynchronous preset and asynchronous reset input terminals, i.e., a programmable storage element. Asynchronous preset line 410A1-i-68 is connected to the asynchronous preset terminal of flip-flop 503 and asynchronous reset product term line 410A1-i-67 is connected to the asynchronous reset terminal of flip-flop 503.

As previously described and illustrated in FIGS. 17A to 17D and 18A to 18D, in each of the programmable logic devices of this invention, each programmable logic block 402 within the device has an asynchronous preset product term line and an asynchronous reset product term line which are connected to the appropriate terminals of each flip-flop 503 in the logic macrocells, including the buried logic macrocells, described more completely below.

Lines CLK0 and CLK1 from dedicated input pins 404A1-3, 404A1-6 are connected to the first and second input terminals respectively of a programmable two-to-one clock selection multiplexer 501. The state of programmable multiplexer 501 is determined by architectural cell 502. When cell 502 is programmed to a logic 0, the signal on line CLK0 is provided to the output line of multiplexer 501, which is connected to the clock input terminal of flip-flop 503. Conversely, when cell 502 is set to a logic 1, the signal on line CLK1 is provided to the clock input terminal of flip-flop 503.

Architectural configuration cell 504 is used to configure flip-flop 503 either as a D type flip-flop or a T type flip-flop. Output terminal Q of flip-flop 503 is connected to a second input terminal of programmable output path selection multiplexer 505. Architectural cell 506 configures multiplexer 505 so that either the signal on the first input terminal, a combinatorial signal, or the signal on the second input terminal, a registered signal, is provided to the output terminal of multiplexer 505.

As illustrated in FIGS. 30A and 30B, when architectural cell 506 is programmed to a logic 1, the signal on the first input terminal from OR gate 500 is supplied to the output terminal of multiplexer 505 so that logic macrocell 412A1 provides a combinatorial output. Conversely, when architectural cell 506 is programmed to a logic 0, the output signal from flip-flop 503 is provided on the output terminal of multiplexer 505 so that logic macrocell 412A1 functions as a registered cell (FIGS. 30C-30F). The signal on the output terminal of multiplexer 505 (FIG. 29A) is provided to line 427A1-i-m which, as previously described, is one of the feedback lines to switch matrix 401A1.

The final structure in logic macrocell 412A1 (FIG. 29A) is a programmable two-to-one polarity selection multiplexer 507 which has a first input terminal connected to the output terminal of multiplexer 505 and a second input terminal, which contains an inverter, that is also connected to the output terminal of multiplexer 505. Architectural cell 508 controls the operation of multiplexer 507.

When cell 508 is programmed to a logic 1, multiplexer 507 provides the signal from multiplexer 505 to the I/O cell. Conversely, when architectural cell 508 is programmed to a logic 0, the inverter inverts the signal from the output terminal of multiplexer 505 so that the complement of the signal from multiplexer 505 is provided to the I/O cell. Therefore, multiplexer 505 determines the polarity of the output signal from logic macrocell 412A1.

In another embodiment (not shown) multiplexer 507 is not included within the logic macrocell. Rather, an Exclusive OR gate, which is placed in the input line to storage element 503 just before the connection in the input line to multiplexer 505, is used to control output signal polarity. Hence, the important aspect is that logic macrocell 412A1 includes a means for controlling the logic signal polarity.

Thus, a logic macrocell, according to this invention, may be configured so that the output signals are either registered or combinational with an active high or an active low polarity. When the logic macrocell is used as a register, the logic macrocell can be further configured as a D type or T type flip-flop. Programmable polarity along with the built in T type flip-flop capability minimizes the number of product terms required for implementing some logic functions.

The possible configurations of logic macrocell 412A1 are shown in more detail on FIGS. 30A through 30F. FIG. 30A illustrates the cell configured as combinatorial cell with an active high polarity while FIG. 30B illustrates the cell configured as a combinatorial cell with an active low polarity. FIGS. 30C and 30D illustrate the cell configured as a registered cell with a D type flip-flop and active high and active low polarity respectively while FIGS. 30E and 30F illustrate the cell as a T type flip-flop with active high and active low polarity respectively.

In FIGS. 30C through 30F, the signals on line CLK0 or line CLK1 may be selected by multiplexer 501 so each of these figures actually represent two possible configurations. Thus, in this embodiment, there are a total of ten possible configurations obtained with the four programmable architectural cells in logic macrocell 412A1, but the four programmable architectural cells can support a total of sixteen possible configurations.

Each output logic macrocell 412A1 provides an output signal to an I/O cell and also sends the output signal to switch matrix 401A1 via dedicated internal feedback line 427A1. The feedback signal is provided for either a registered or a combinatorial signal and is always available regardless of I/O cell configuration, as described more completely below. Since the feedback signal may be either registered or combinatorial, the feedback signal allows for buried sequential or combinational functions and consequentially frees I/O pins for use as input pins only. As previously described, each logic macrocell is decoupled from an I/O pin by an I/O macrocell.

In another embodiment (FIG. 29B), programmable flip-flop 503 is replaced by a programmable storage element 503A that may be configured as any one of a D-type flip-flop, a T-type flip-flop or a latch. Architectural cells 504 and 506 are used to configure multiplexer 505 and the programmable storage element so that the signal on the output terminal of multiplexer 505 is one of: (i) a D-type flip-flop output signal; (ii) a T-type flip-flop output signal; (iii) a latch output signal; or (iv) a combinatorial output signal. This configuration is equivalent to the storage element in one embodiment of the macrocells of PLDs 210, 220 and 230.

In yet another embodiment (not shown), programmable flip-flop 503 is replaced with a programmable storage element which functions as one of a T-type flip-flop, a D-type flip-flop, a J-K flip-flop, an RS flip-flop, or a transparent latch. Since in this embodiment the storage element functions in one of four modes, two architectural cells are required for the storage element. Also, an additional input line or lines may be required to support the function of the J-K flip-flop or the RS flip-flop. The storage element operates as a T-type flip-flop when both cells provide a logical zero; as a D-type flip-flop when the first cell provides a logical one and the second cell provides a logical zero; as a J-K flip-flop when the first cell provides a logical zero and the second cell provides a logical one; and as RS flip-flop when both cells provide a logical one.

Logic macrocells 412A2 and 412A3 (FIG. 29C) are similar to logic macrocell 412A1-A (FIG. 29B). However, two-to-one multiplexer 501 with one architectural cell in PLD 110 is replaced with a four-to-one multiplexer with two architectural cells in logic macrocells 412A2 and 412A3. Recall that in devices 120 and 130 four of the dedicated input pins may be used either as pins for a dedicated input signal or pins for a clock signal. Accordingly, logic macrocells 412A2 and 412A3 may be driven by any one of the four clock signals.

Thus, PLDs 120 and 130 provide significantly greater flexibility with respect to clocking than PLD 110 where each macrocell had only two available clock sources. The number of registers available in PLD 130 with the four clock sources for each register allows system designers to implement flexible and multiple state machines in a single device. Also, in PLDs 120 and 130, which contain logic macrocells 412A2 and 412A3 respectively, storage element 503 and multiplexer 505 are included in a single component 503A with two architectural cells, but the same combination of functions is provided as in logic macrocell 412A1.

As previously described, programmable logic block 402B of second family 400B of programmable logic devices 210, 220 and 230 of this invention includes a plurality of logic output macrocells 412BA and a plurality of buried logic macrocells 412BB. Logic macrocell 412BA1 for PLD 210, sometimes referred to as an output logic macrocell, is similar to logic macrocell 412A1-A (FIG. 29B) of PLD 110 and the description of macrocell 412A1-A is incorporated herein by reference.

Buried logic macrocell 412BB1 (FIG. 31A) is also similar to output logic macrocells 412A1-A, 412BA1 (FIG. 29B) except buried logic macrocell 412BB does not have polarity control multiplexer 507. The output signal from buried logic macrocell 412BB1 (FIG. 31A) is an internal feedback signal on line 427B1-i-m to switch matrix 401B1. Buried logic macrocells 412BB1 of this invention increase the logic capability of programmable logic device 210 and provide higher silicon efficiency than would be obtained without the cells.

In buried logic macrocell 412BB1, OR gate 500 has an output line which is connected to a first terminal of a programmable input signal selection two-to-one multiplexer 509. The input line from I/O pin is connected to the second input terminal of programmable multiplexer 509. Architectural configuration cell 510 is used to configure multiplexer 509 so that either the signal from I/O pin or from OR gate 500 is provided to the output terminal of multiplexer 509.

The output terminal of multiplexer 509 is connected to the input terminal D/T/L of programmable storage element 503 and to the second input terminal of multiplexer 505. The remainder of buried logic macrocell 412BB is configured as previously described for output logic macrocell 412A1.

Buried logic macrocell 412BB1 has fourteen different configurations. Buried logic macrocell 412BB1 can provide (i) a combinatorial output from logic allocator 411B1 to switch matrix 401B1 (FIG. 32A), (ii) a registered D type flip-flop signal to switch matrix 401B1 from logic allocator 411B1 (FIG. 32B), (iii) a registered T type flip-flop signal to switch matrix 401B1 from logic allocator 411B1 (FIG. 32C), or (iv) a latched signal to switch matrix 401B1 from logic allocator 411B1 (FIG. 32D).

Similarly, the signal on the I/O pin can be selected by multiplexer 509 so that buried logic macrocell provides (i) a combinatorial input signal to switch matrix 401B1 (FIG. 32H), (ii) a registered input signal from a D type flip-flop to switch matrix 401B1 (FIG. 32E), (iii) a registered input signal from a T type flip-flop to switch matrix 401B1 (FIG. 32F), or a latched input signal to switch matrix 401B1 (FIG. 32G). Each of the registered and latched signals can be clocked/latched with either of the signals on lines CLK0/LE0, CLK1/LE1. Alternatively, buried logic macrocells 412BB1 could include the alternative storage elements described above for flip-flop 503 in logic output macrocell 412A1 and that description is incorporated herein by reference.

A significant feature of buried logic macrocell 412BB1 is the dual mode of operation, i.e., the buried logic macrocell's ability to function either as an output cell with feedback to switch matrix 401B1 or as a registered/latched input cell. Buried logic macrocell 412BB1 along with the bypassable registered/latched input increases significantly the utilization and silicon efficiency of programmable logic device 210B. Both dedicated input pin signals and buried logic macrocell feedback signals are available to switch matrix 401B at all times. This permits the simultaneous use of either the dedicated input pin signals and the registered/latched input signals from buried logic macrocells, or the dedicated input pin signals plus the buried registered/latched feedback signals.

Both output logic macrocells 412A1, 412BA1 and buried logic macrocells 412BB1 are clocked/latched on an individual macrocell basis by a signal from one of the two synchronous clock input pins. This clocking/latch enabling allows the user to implement flexible and multiple state machines in a single device. Further, even if either of the clock/latch enable input pins is used as a clock/latch enable signal source, the pin is still available as an input pin to the switch matrix.

Buried logic macrocells 412BB2 and 412BB3 (FIG. 31B) are similar to logic macrocell 412BB1. However, two-to-one multiplexer 501 with one architectural cell in PLD 210 is replaced with a four-to-one multiplexer with two architectural cells in logic macrocells 412BB2 and 412BB3. Similarly output logic macrocells 412BA2 and 413BA3 are equivalent to logic macrocell 412A2 (FIG. 29C). Recall that in devices 220 (FIGS. 15A to 15D) and 230 (FIGS. 16A to 16D), four of the dedicated input pins may be used either as pins for a dedicated input signal or pins for a clock signal. Accordingly, logic macrocells 412BA2, 412BB2, 412BA3 and 412BB3 may be driven by any one of the four clock signals. Thus, PLDs 220 and 230 provide significantly greater flexibility with respect to clocking than PLD 210 where each macrocell had only two available clock sources.

In this embodiment, the latch in programmable element 503 has an input terminal, an output terminal, a latch enable terminal, an asynchronous preset terminal and an asynchronous reset terminal. The latch is a transparent latch. When the signal on the latch enable terminal is low, the latch is in the transparent mode, and the signal on the output terminal responds to the signal on the input terminal. When the signal on the latch enable terminal is high, the output signal is latched to retain the data set up on the input terminal. The signals on the preset terminal and the reset terminal dominate when either signal is active in conjunction with a high signal on the latch enable terminal. The other modes of operation associated with other combinations of signals on the latch enable, preset, and reset terminals are defined as "other states" or "illegal states."

                  TABLE 4                                                          ______________________________________                                                Latch   Asyn     Asyn                                                          Enable  RESET    PRESET                                                 Mode # (LE)    (AR)     (AP)   Latch Mode                                      ______________________________________                                         Allowed States                                                                 1      0       0        0      Transparent Mode                                2      1       0        0      Latched Mode or                                                                Storage Mode                                    3      1       0        1      SET mode, Q = H                                 4      1       1        0      RESET mode, Q = L                               Other States                                                                   5      1       1        1      RESET Dominates                                 6      0       0        1      SET Dominates, Q = H                            7      0       1        0      Latch output follows                                                           Data Input                                      8      0       1        1      Latch output follows                                                           Data Input                                      ______________________________________                                    

The particular bit sequences in Table 4 are illustrative only of one embodiment of this invention and are not intended to limit the invention to the particular embodiment disclosed. In view of this disclosure, those skilled in the art will be able to configure the programmable features of this invention using a variety of different values for the programming bits.

As previously described, all the logic macrocells including any buried logic macrocells in the programmable logic block are controlled by a common asynchronous reset product term and a common asynchronous preset product term. Thus, for each programmable logic block, all the flip-flops in the logic macrocells whether in an output logic macrocell or a buried logic macrocell are simultaneously initialized.

In this embodiment, the primary factors in the architecture are performance and cost in an optimal silicon efficient structure. For example, many programmable logic devices support both synchronous and asynchronous logic applications on a single chip. However, synchronous and asynchronous logic applications needs are different. While this configuration results in a more flexible structure, the configuration invariably requires compromise which in turn results in an inefficient structure in terms of use, speed, and silicon efficiency.

One specific example is the fixed allocation of individual reset, preset, clock, and output enable product terms per macrocell. While such an allocation of product terms provides a great deal of flexibility, a fixed allocation of four product terms per macrocells--a very expensive proposition for synchronous logic applications--is required. The control product terms essentially are wasted for synchronous logic applications. Also, individual product term allocation requires compromises for clock selection for logic macrocells because the macrocells are limited to only one clock signal from an external synchronous clock pin, which, in turn, restricts the device to a single synchronous state machine.

I/O macrocell 413 of this invention is illustrated in FIG. 33. I/O macrocell 413 has a single three-state buffer 540 coupled to I/O pin 541. The input terminal of three-state buffer 540 is connected to output line from an output logic macrocell. The control terminal of buffer 540 is connected to the output line of a four-to-one programmable multiplexer 542. The output terminal of buffer 540 is also coupled to switch matrix 401A in the first family 400A of devices and to buried macrocell multiplexer 509 and switch matrix 401B in the second family 400B of devices.

Two output enable product terms are connected to the first two inputs of four-to-one multiplexer 542. The third input terminal is tied to power supply voltage V_(cc) and the fourth terminal is grounded. Multiplexer 542 selectively provides an output enable signal to buffer 540.

Four-to-one multiplexer 542 has two architectural cells 543, 544. When first cell 543 is programmed to a logic 0 and second cell 544 is programmed to a logic 1, the first output enable product term is supplied to the control terminal of tristate buffer 540. When both architectural cells 543, 544 are programmed to a logic 1, the second output enable product term i supplied to the output control terminal of tristate buffer 540. When architectural cell 543 is programmed to a logic 1 and cell 544 to a logic 0 power supply voltage V_(cc) is supplied to the terminal of buffer 540 and when both of the architectural cells 543, 544 are programmed to a logic 0 the terminal of tristate buffer 540 is grounded.

When power supply voltage V_(cc) is supplied to tristate buffer 540, buffer 540 is permanently enabled for use as an output buffer and conversely when the control terminal is grounded, buffer 540 is tristated so that I/O pin 541 functions permanently as an input pin. When either of the output enable terms is applied to the control terminal, the I/O pin functions as a bidirectional I/O pin which is controlled by the product term.

As previously explained, the two product terms are common to a bank of eight I/O cells in one embodiment, and a bank of six I/O cells in another embodiment. In both embodiments, the two product terms permit the bank of I/O cells to be configured as two separate partial banks within the bank of I/O macrocells. One of the product terms controls the first partial bank of I/O macrocells and the other product term controls the second partial bank of I/O macrocells. Thus, the use of two product terms for each I/O macrocell significantly enhances the capability of the PLDs 400.

An important feature of the I/O cell structure of this invention is that this structure decouples logic macrocells 412 from I/O pins 403. The decoupling of logic macrocells 412 from 1/0 pins 403 has two major benefits. First, the decoupling provides dual feedback capability for programmable switch matrix 401 and second the decoupling moves the connectivity issue to switch matrix 401 where it belongs rather than prefixing at the pin. Dual feedback capabilities are beneficial for applications requiring large amounts of buried logic such as counters, shift registers, and complex state machines and I/O intensive applications requiring large amounts of pins, reserving the macrocell functions for buried logic.

Switch interconnect matrix 401 is arranged so that each signal passing through this matrix passes through a fixed number of interconnect elements within the switch matrix. This insures that the time delays for all signals passing through switch matrix 401 are substantially the same and allows resynchronization, if desired, of groups of contemporaneous signals passing through switch matrix 401. Specifically, the time delay for a signal through the switch matrix is a fixed, uniform path independent delay irrespective of the signal's origin. Hence, a dedicated input pin signal, an I/O pin input signal, and a feedback signal, all see the same time delay in traversing through the switch matrix.

To achieve maximum speed through switch matrix 401, the matrix has been purposely not implemented as a full cross-point switch. The switch matrix could be implemented as a full cross-point switch to achieve enhanced functionality. However, the enhanced functionality of the full cross-point switch matrix results in diminished speed performance, an increased die size, and potentially wasted silicon.

Switch matrix 401 was selected to provide a balance between functionality, speed performance and die size. Switch matrix 401 is structured as a single, centralized switch to achieve the uniform, fixed delay time for all signal paths through switch matrix 401, as described above. However, switch matrix 401 may also be implemented as multiple hierarchial decentralized switches. In view of the description of switch matrix 401 of this invention and the full cross-point switch matrix, other switch matrices, having varying degrees of functionality, speed and die size, could be designed and implemented by those skilled in the art.

Switch matrix 401AI for PLD 110 of programmable logic devices 400 of this invention is illustrated in FIG. 34. In FIG. 34, the horizontal lines represent signal input lines to switch matrix 401A1. The vertical lines represent the input lines to programmable logic blocks 402A1-1, 402A1-2. The circles at the intersections of the horizontal and vertical lines represent programmable connections. Specifically, as explained more completely below, switch matrix 401AI includes a multiplicity of four-to-one programmable multiplexers and a multiplicity of five-to-one programmable multiplexers.

The upper most group of eight horizontal lines are lines 428A1-1 (FIG. 34) which provide input signals from I/O pins 403A1-17 to 403A1-32 (FIG. 11). The next group of sixteen horizontal lines are lines 427A1-1-1 to 427A1-1-16 (FIG. 34) from logic macrocells 412A1-1 (FIG. 11). Accordingly, these lines provide feedback signals to switch matrix 401A1 from logic macrocells 412A1-1. The third group of sixteen horizontal lines are lines 428A1-2 (FIG. 34) from I/O pins 403A1-1 to 403A1-16 (FIG. 11) and the fourth group of sixteen horizontal lines are lines 427A1-2 (FIG. 26) from logic macrocells 412A1-2. The next pair of lines are dedicated input lines from dedicated input pins 404A1-1 and 404A1-2. The bottom four horizontal lines are connected to the two dedicated input pins 404A1-4, 404A1-5 and the two clock/input pins 404A1-3 and 404A1-6.

The first twenty-two vertical lines 426A1-1-1 through 426A1-1-22 from the left-hand side of switch matrix 401A are connected to input lines 426A1-1 to programmable logic block 402Ai-1. The other twenty-two vertical lines on the right-hand side of switch matrix 401AI are input lines 426A1-2 of programmable logic block 402A1-2.

The portion of switch matrix 401AI associated with a programmable logic block 402A1-i has a total of twenty programmable multiplexers, one which drives each input line of the product term array and which programmably couples selected switch matrix input lines, the horizontal lines in FIG. 34, to selected switch matrix output lines, the vertical lines in FIG. 34, which in turn are the input lines to a programmable logic block. Thus, switch matrix 401AI consists of a total of forty programmable multiplexers.

In each group of twenty programmable multiplexers associated with the input lines of programmable logic block, sixteen of the multiplexers are four-to-one multiplexers, and four are five-to-one multiplexers. Two of the input lines for each programmable logic block are connected directly to dedicated input pins by switch matrix 401A1. In FIG. 34, each vertical line is either an output line from one of the multiplexers or one of the two fixed lines. The circles on a vertical line represent programmable connections between the input lines and the output line of the particular multiplexer.

For example, the ninth vertical line from the left-hand side of the matrix is input line 426A1-1-9 to programmable logic block 402A1-1 and is the output line of a programmable four-to-one multiplexer in switch matrix 401A1. The input lines to this multiplexer are line 428A1-1-9 from the ninth I/O pin of programmable logic block 402A1-1, line 427A1-1-1 from the first logic macrocell 402A1-1 and the corresponding lines from the second programmable logic block 402A1-2.

Thus, sixteen of the input signals for both programmable logic blocks 402A1-1, 402A1-2 are derived from four different sources, i.e., two I/O pin sources and two macrocell feedback sources rotated to allow dual feedback capability.

More specifically, each four-to-one programmable multiplexer has two architectural cells which are used to configure the multiplexer so that only one of the input lines is connected to the output line. The architectural cells provide an input select signal to the multiplexer. The resource selection for each group of multiplexers is presented in Tables 5 and 6.

                  TABLE 5                                                          ______________________________________                                         Four-to-One Programmable Multiplexer Signal                                    Selection in Switch Matrix 401A1 of Family 400A                                Architectural                                                                             Architectural                                                                               Global Signal                                          Cell 1     Cell 2       Selections                                             ______________________________________                                         0          0            I/O pin input signals                                                          from PLB 402A1-1                                       0          1            Feedback signals                                                               from logic                                                                     macrocells in PLB                                                              402A1-1                                                1          0            I/O pin input signals                                                          from PLB 402A1-2                                       1          1            Feedback signal                                                                from logic                                                                     macrocells in PLB                                                              402A1-2                                                ______________________________________                                    

Note in Table 6, the multiplexers receive input signals from only a single programmable logic block so that only the multiplexers associated with block 402A1-1 are given in Table 6. The architectural cells configurations for block 402A1-2 is the same as that shown for block 402A1-1 except the sources are from block 402A1-2.

                  TABLE 6                                                          ______________________________________                                         Signal Selection for Five-to-One Programmable                                  Multiplexer in Switch Matrix 401A1 of Family 400A.                             Architectural                                                                           Architectural                                                                             Architectural                                                                             Global Signal                                   Cell 1   Cell 2     Cell 3     Selections                                      ______________________________________                                         0        0          0          I/O pin input                                                                  signals from                                                                   PLB 402A1-1                                     0        1          0          Feedback signals                                                               from logic                                                                     macrocells in PLB                                                              402A1-1                                         1        0          0          I/O pin input                                                                  signals from                                                                   PLB 402A1-1                                     1        1          0          Feedback signals                                                               from logic                                                                     macrocells in PLB                                                              402A1-1                                         0        0          1          Signal from                                                                    dedicated input                                                                pin                                             ______________________________________                                    

The input signal sources to switch matrix 401A1 are appropriately rotated so that for any logic macrocell and the I/O pin associated with that logic macrocell, both the logic macrocell feedback signal and the signal on the corresponding I/O pin are available to each programmable logic block in device 110.

For example, the signal on the first I/O pin is an input to the first four-to-one multiplexer while the feedback signal is an input to the ninth four-to-one multiplexer. Thus, this rotation allows buried registered capability without increasing the size of the product term array. Hence, unlike prior art devices, the product term array size is independent of the number of logic macrocells.

Also notice that each programmable logic block may receive the same input signals or different input signals. This allows the structure to function either as a monolithic array with a maximum of twenty-two inputs common to each array or two separate relatively independent split arrays with a total maximum number of forty-two input signals.

An alternate representation of switch matrix 401A1 is illustrated in FIG. 35A and 35B. For ease of presentation, blocks 402A1-1 and 402A1-2 are represented as blocks "A" and "B" respectively. Similarly, logic macrocell 412A1-1-1 becomes A1 and logic macrocell 412A1-2-1 becomes B1 so that the macrocells in block 401A1-1 range from macrocell A1 to macrocell A16 and in block 402A1-2 from macrocell B1 to B16. The feedback lines are represented by the macrocell number. The I/O pin associated with a macrocell is represented by the macrocell number followed by a carat " ". Dedicated input pins 404A are numbered I1 to I6.

In programmable logic devices 110, switch matrix 401A1 drove twenty-two input lines for each programmable logic block in the device. The important aspect, as previously described, is that the number of input lines is fixed and does not change with changes in the number of logic macrocells or dedicated input pins.

The major thrust for the family of PLDs of this invention is speed. Hence, each of the components in the devices were optimized for speed, even at some expense of flexibility. In particular, interconnect architecture plays an extremely important role for the performance of high density PLDs. For the segmented block based PLD architecture of this invention, there are at least two approaches for implementing interconnects, a fully populated cross-point switch interconnect array or a sparsely populated switch matrix.

As previously described, a fully populated interconnect array causes significant speed degradation and also possibly results in higher die cost. Hence switch matrix 401 is a partially populated structure and in one embodiment is based on a series of multiplexers. Since switch matrix 401 is not implemented as a fully populated cross-point switch (or interconnect array), signal routing for the PLDs of this invention is essentially affected by two factors: the number of input lines to the programmable array in the programmable logic block and the switch matrix multiplexer size for each of such input lines.

As described above, PLD 110 has 22 input lines to the programmable logic block. Also, the switch matrix multiplexers for PLD 110 are implemented as 4:1 and 5:1 multiplexers. While this is acceptable for low-density PLDs, higher density PLDs 120, 130, 220, and 230 of this invention have even greater routability.

To ensure greater routability, both the number of programmable input lines and the switch multiplexer size are increased for these PLDs. However, both a larger number of programmable array input lines and larger switch matrix multiplexer size incur both a speed penalty and a die size penalty. For example, in one embodiment for the technology described above, increasing the number of programmable array input lines by 4 introduces a speed penalty of about 0.4 to 0.6 nanoseconds and a potential die size increase of about 6,000 to 7,000 square mils. Therefore, according to the principles of this invention, a balance is obtained between die size, speed and routability.

Preferably for high density PLDs 120, 130, 220 and 230 of this invention, each routable signal must have more than 2.5 ways to enter each programmable logic block, i.e., a routability factor of at least 2.5. More preferably, each signal is routable in at least 3 ways.

Obtaining the signal routability of at least 2.5 can be accomplished, for example, either by adjusting the number of input lines to the programmable array or the switch matrix multiplexer size. For a fixed number of programmable array input lines, i.e. 26 input lines, the switch matrix multiplexer size is selected to provide at least the 2.5 routability factor. Specifically, in this embodiment, the routability factor for switch matrix 401 is: ##EQU1##

For PLDs 110, 120, 130, 210, 220 and 230 the total number of routable signals to switch matrix 401 is the sum of dedicated input pin signals, logic macrocell feedback signals and I/O pin signals, which is the maximum number of signal sources for the switch matrix. Table 7 gives the multiplexer size (mux size), number of programmable array input lines and the total number of routable signals for each of the PLDs of this invention.

                  TABLE 7                                                          ______________________________________                                                110   210     120     220   130   230                                          Package Size                                                                   44-pin                                                                               44-pin  68-pin  68-pin                                                                               84-pin                                                                               84-pin                                ______________________________________                                         # of Input                                                                              22      22      26    26    26    26                                  Lines/BLK                                                                      Switch   4:1     12:1    16:1  16:1  16:1  16:1                                Matrix (SM)                                                                    Mux Size                                                                       # of IO  32      32      48    48    64    64                                  signals                                                                        # of     6       6       8     8     6     6                                   Dedicated                                                                      Input signals                                                                  # of Macro-                                                                             32      64      48    96    64    128                                 cell Feedback                                                                  Signals                                                                        Max # of 70      102     104   152   134   198                                 Signal                                                                         Sources for                                                                    SM                                                                             # of Signal                                                                             70      102     104   152   134   150                                 Sources used                                                                   for SM                                                                         Max # of 1.14    2.58    4.0   2.73  3.1   2.77                                Ways a signal                                                                  can be routed                                                                  ______________________________________                                    

In PLD 120, switch matrix 401A2 routes 26 signals to each programmable logic block 402A2. The 26 signals are derived from a maximum of 104 global signals. Further, as shown in Table 7, each of the input signals provided by switch matrix 402A2 is derived from a 16 to 1 multiplexer. Thus, the 104 signal sources are grouped into 16 bands with approximately 6.5 signals in each band. One signal may be shared between two or more bands. Thus, for comparison of band structures, a fraction of the signal is assigned to each band that shares the signal. Thus, the signals in a band may include a fraction of a signal. FIG. 36 illustrates the set of signal bands that are used for all four programmable logic blocks in PLD 120.

For ease of representation, programmable logic blocks 402A2-1, 402A2-2, 402A2-3, and 402A2-4, are represented as blocks "A", "B", "C", and "D", respectively. Similarly, logic macrocell 412A2-1-1 becomes "A0", logic macrocell 412A1-1-12 becomes "A11", and logic macrocell 412A2-2-1 becomes "B0". Thus, the logic macrocells in block 402A2-1 range from macrocell A0 to macrocell A11, and block 402A2-2 from macrocell B0 to B11, and block 402A2-3 from macrocell C0 to C11, and in block 402A2-4 from macrocell D0 to D11. The feedback lines to switch matrix 401A2 are represented by the macrocell number. The I/O pin associated with the macrocell is represented by the macrocell number followed by a carat " ". Dedicated input pins 404A2 are numbered I0 through I7 respectively.

In one embodiment, the 104 signals are grouped into 16 signal bands and one signal from each band is programmably selectable as an input signal to one of the 16:1 multiplexers of switch matrix 401A2. FIG. 37 illustrates graphically the sixteen bands where each band has 6.5 signals and the output line from the band is an input line to a 16:1 multiplexer. The signals have been grouped in bands to maximize routability and to ease the layout of PLD 120. The signals in a band are selected based upon the physical locations of the dedicated input pins as well as layout considerations necessary to maintain speed performance and ease of manufacture.

Notice that the signal sources in a band are appropriately rotated to allow both the macrocell feedback and the corresponding I/O feedback to be available for each programmable logic block. This rotation allows the buried register capability without increasing the array size and is one of the important features of this invention. An important aspect of this invention is the arrangement of signals within a band and the rotation of signals in a band to allow maximum flexibility and routability for getting signals from dedicated input pins, I/O pins, macrocell feedback lines, and buried macrocell feedback lines simultaneously to a programmable logic block.

FIGS. 38A to 38D illustrate the actual switch matrix signal patterns for all four programmable logic blocks 402A2 of PLD 120. The columns in FIGS. 38A to 38D are the signals in the band which are rotated within the column, as described above, and each row is the input signals to a 16 to 1 multiplexer that provides the input signal on the input line indicated in the left hand column. Note, for ease of representation, FIGS. 38A to 38D include the input line column in each figure. However, only a single input signal is provided by each row of the table shown in the four figures.

According to the principles of this invention, the 26 input signals for each programmable logic bloc 402A2-i may be unique or the same for all four blocks. This allows PLD 120 to function either as a monolithic array with a maximum of 26 input signals, or four separate relatively independent split-arrays with a total maximum number of input signals of 104 at a given instant.

In PLD 130, switch matrix 401A3 also routes 26 signals to each programmable logic block 402A3. The 26 signals are derived from a maximum of 134 global signals. Further, as shown in Table 7, each of the input signals provided by switch matrix 402A3 is derived from a 16 to 1 multiplexer. Thus, the 134 signal sources are grouped into 16 bands with approximately 8.5 signals in each band. FIG. 39 illustrates the set of signal bands that are used for all four programmable logic blocks in PLD 130.

For ease of representation, programmable logic blocks 402A3-1, 402A3-2, 402A3-3, and 402A3-4, are represented as blocks "A", "B", "C", and "D", respectively. Similarly, logic macrocell 412A3-1-1 becomes "A0", logic macrocell 41231-1-16 becomes "A15", and logic macrocell 412A3-2-1 becomes "B0". Thus, the logic macrocells in block 402A3-1 range from macrocell A0 to macrocell A15, in block 402A3-2 from macrocell B0 to B15, in block 402A3-3 from macrocell C0 to C15, and in block 402A3-4 from macrocell D0 to D15. The feedback lines to switch matrix 401A3 are represented by the macrocell number. The I/O pin associated with the macrocell is represented by the macrocell number followed by a carat " ". Dedicated input pins 404A3 are numbered I0 through I5 respectively.

In one embodiment, the 134 signals are grouped into 16 signal bands and one signal from each band is an input signal to one of the 16:1 multiplexer of switch matrix 401A2. FIG. 40 illustrates graphically the sixteen bands with each having 8.5 signals. The output line from the band is an input line to a 16:1 multiplexer. The signals have been grouped in bands to maximize routability and to ease the layout of PLD 130. Notice that the signal sources in a band are appropriately rotated to allow both the macrocell feedback and the corresponding I/O feedback to be available for each programmable logic block. This rotation allows the buried register capability and signal routability without increasing the array size and is one of the important features of this invention.

FIGS. 41A to 41D illustrate the actual switch matrix signal patterns for all four programmable logic blocks 402A3 of PLD 130. The columns in FIGS. 41A to 41D are the signals in the band which are rotated within the column, as described above, and each row is the input signals to a 16 to 1 multiplexer that provides the input signal on the input line indicated in the left hand column. Note, for ease of representation, FIGS. 41A to 41D include the input line column in each figure. However, only a single input signal is provided for each row of the table as shown in the four figures.

According to the principles of this invention, the 26 input signals for each programmable logic block 402A3-i may be unique or the same for all four blocks. This allows PLD 130 to function either as a monolithic array with a maximum of 26 input signals, or four separate relatively independent split-arrays with a total maximum number of 104 input signals out of a possible 134 signals at a given instant.

As described above PLDs 120, 130, 220 and 230 have an increased number of input lines to programmable array 410 and a switch matrix 402 with 16:1 multiplexers to provide a rotability factor of at least 2.5 for these high density devices. However, PLD 210 is a lower density device compared to the other devices of this invention and so in PLD 210, switch matrix 401B1 routes 22 signals to each programmable logic block 402B1. The 22 signals are derived from a maximum of 102 global signals. Further, as shown in Table 7, each of the input signals provided by switch matrix 402B1 is derived from a 12 to 1 multiplexer. Thus, the 102 signal sources are grouped into 12 bands with approximately 8.5 signals in each band. FIG. 42 illustrates the set of signal bands that are used for all four programmable logic blocks in PLD 210.

For ease of representation, programmable logic blocks 402B1-1, 402B1-2, 402B1-3, and 402B1-4, are represented as blocks "A", "B", "C", and "D", respectively. Similarly, logic macrocell 412BA1-1-1 becomes "A0", buried logic macrocell 412BB1-1-1 becomes "A1" logic macrocell 412BB1-1-8 becomes "A15", and logic macrocell 412BA1-2-1 becomes "B0". Thus, the logic macrocells in block 402B1-1 range from macrocell A0 to macrocell A15, and block 402B1-2 from macrocell B0 to B15, and block 402B1-3 from macrocell C0 to C15, and in block 402B1-4 from macrocell D0 to D15 where the even numbers are output logic macrocells and the odd numbers are buried logic macrocells. The feedback lines to switch matrix 401B1 are represented by the macrocell number. The I/O pin associated with the output logic macrocell is represented by the macrocell number followed by a carat " ". Dedicated input pins 404B1 are numbered I0 through I5 respectively.

In one embodiment, the 102 signals are grouped into 12 signal bands and one signal from each band is an input signal to one of the 12:1 multiplexers of switch matrix 401B1. FIG. 43 illustrates graphically the twelve bands with each band having 8.5 signals. The output line from the band is an input line to a 12:1 multiplexer. The signals have been grouped in bands to maximize routability and to ease the layout of PLD 210. Notice that the signal sources in a band are appropriately rotated to allow both the macrocell feedback and the corresponding I/O feedback to be available for each programmable logic block. This rotation allows the buried register capability without increasing the array size and is one of the important features of this invention.

FIGS. 44A to 44C illustrate the actual switch matrix signal patterns for all four programmable logic blocks 402B1 of PLD 210. The columns in FIGS. 44A to 44C are the signals in the band which are rotated within the column, as described above, and each row is the input signals to a 12 to 1 multiplexer that provides the input signal on the input line indicated in the left hand column. Note, for ease of representation FIGS. 44A to 44C includes the input line column in each figure. However, only a single input signal is provided by each row of the table shown in the four figures.

According to the principles of this invention, the 22 input signals for each programmable logic block 402B1-i may be unique or the same for all four blocks. This allows PLD 210 to function either as a monolithic array with a maximum of 22 input signals, or four separate relatively independent split-arrays with a total maximum number of 88 input signals out of a possible 102 signals.

In PLD 220, switch matrix 401B2 routes 26 signals to each programmable logic block 402B2. The 26 signals are derived from a maximum of 152 global signals. Further, as shown in Table 7, each of the input signals provided by switch matrix 402B2 is derived from a 16 to 1 multiplexer. Thus, the 152 signal sources are grouped into 16 bands with approximately 9.5 signals in each band. FIG. 45 illustrates the set of signal bands that are used for all eight programmable logic blocks in PLD 220.

For ease of representation, programmable logic blocks 402B2-1, 402B2-2, . . . , 402B2-8, are represented as blocks "A", "B", . . . , "H", respectively. Similarly, logic macrocell 412BA2-1-1 becomes "A0", buried logic macrocell 412BB2-1-1 becomes "A1", logic macrocell 412BB2-1-6 becomes "A11", and logic macrocell 412BA2-2-1 becomes "B0". Thus, the logic macrocells in block 402B2-1 range from macrocell A0 to macrocell All, in block 402B2-2 from macrocell B0 to B11, . . . , and in block 402B2-8 from macrocell H0 to H11 where the even numbers are output logic macrocells and the odd numbers are buried logic macrocells. The feedback lines to switch matrix 401B2 are represented by the macrocell number. The I/O pin associated with the output logic macrocell is represented by the macrocell number followed by a carat " ". Dedicated input pins 404B2 are numbered I0 through I7 respectively.

In one embodiment, the 152 signals are grouped into 16 signal bands and one signal from each band is an input signal to one of the 16:1 multiplexers of switch matrix 401B2. FIG. 46 illustrates graphically the sixteen bands each have 9.5 signals and the output from the band is an input line to a 16:1 multiplexer. The signals have been grouped in bands to maximize routability and to ease the layout of PLD 220. Notice that the signal sources in a band are appropriately rotated to allow both the macrocell feedback and the corresponding I/O feedback to be available for each programmable logic block. This rotation allows the buried register capability without increasing the array size and is one of the important features of this invention.

FIGS. 47A to 50D illustrate the actual switch matrix signal patterns for all eight programmable logic blocks 402B2 of PLD 220. The columns in FIGS. 47A to 50D are the signals in the band which are rotated within the column, as described above, and each row is the input signals to a 16 to 1 multiplexer that provides the input signal, on the input line indicated in the left hand column. Note, for ease of representation FIGS. 47A to 50D includes the input line column in each figure. However, only a single input signal is provided by each row of the table as shown in the four figures representing this portion of switch matrix 402B2.

In particular, FIG. 47A to FIG. 47D represent the portions of the switch matrix that drive programmable logic block 402B2-1 and 402B2-8. FIG. 48A to FIG. 48D represent the portions of the switch matrix that drive programmable logic blocks 402B2-2 and 402B2-7. FIG. 49A to FIG. 49D represent the portions of the switch matrix that drive programmable logic blocks 402B2-3 and 402B2-6. FIG. 50A to FIG. 50D represent the portions of the switch matrix that drive programmable logic blocks 402B2-4 and 402B2-5.

According to the principles of this invention, the 26 input signals for each programmable logic block 402B2-i may be unique or the same for all eight blocks. This allows PLD 220 to function either as a monolithic array with a maximum of 26 input signals, or eight separate relatively independent split-arrays with a total maximum number of input signals of 152 at a given instant.

In PLD 230, switch matrix 401B3 routes 26 signals to each programmable logic block 402B3. The 26 signals are derived from a maximum of 150 global signals rather than the 198 possible signals. Further, as shown in Table 7, each of the input signals provided by switch matrix 402B3 is derived from a 16 to 1 multiplexer. Thus, the 150 signal sources are grouped into 16 bands with approximately 9.5 signals in each band.

For ease of representation, programmable logic blocks 402B3-1, 402B3-2, . . . , 402B3-8, are represented as blocks "A", "B", . . . , "H", respectively. Similarly, logic macrocell 412BA2-1-1 becomes "A0", buried logic macrocell 412BB2-1-1 becomes "A1" logic macrocell 412BB2-1-8 becomes "A15", and logic macrocell 412BA2-2-1 becomes "B0". Thus, the logic macrocells in block 402B2-1 range from macrocell A0 to macrocell A15, in block 402B2-2 from macrocell B0 to B15, . . . , and in block 402B2-8 from macrocell H0 to H15 where the even numbers are output logic macrocells and the odd numbers are buried logic macrocells. The feedback lines to switch matrix 401B3 are represented by the macrocell number. The I/O pin associated with the output logic macrocell is represented by the macrocell number followed by a carat " ". Dedicated input pins 404B3 are numbered I0 through I5 respectively.

FIG. 51A illustrates the set of signal bands that are used for programmable logic blocks 402B3-1 and 402B3-8. FIG. 51B illustrates the set of signal bands that are used for programmable logic blocks 402B3-2 and 402B3-7. FIG. 51C illustrates the set of signal bands that are used for programmable logic blocks 403B3-3 and 402B3-6 while FIG. 51D illustrates the set of signal bands for programmable logic blocks 403B3-4 and 402B3-5. Thus, there are four sets of signal bands for PLD 230, one set for each pair of blocks. This arrangement of bands was used because each programmable logic block derives the 26 input signals from a maximum of 150 signals rather than all 198 possible signals. The smaller number of signals was used to maintain the speed performance of PLD 230. The 150 signals provide adequate flexibility and are chosen to provide a routability factor of at least 2.5.

As illustrated in FIGS. 51A to 51D, the 150 signal sources for the bands have 134 common signal sources for the programmable logic blocks consisting of six dedicated input pin signals, 64 I/O pin feedback signals and 64 output macrocells feedback signals. The other 16 signal sources are different for each pair of programmable logic blocks. These 16 signals are the 8 buried macrocell feedback signals from each block in the pair of programmable logic blocks.

In one embodiment, the 150 signals are grouped into 16 signal bands and one signal from each band is an input signal to one of the 16:1 multiplexers of switch matrix 401B3. FIGS. 52A-52D illustrate graphically the sixteen bands with each band having 9.5 signals. The output line from the band is a n input line to a 16:1 multiplexer. The signals have been grouped in bands to maximize routability and to ease the layout of PLD 230. Notice that the signal sources in a band are appropriately rotated to allow both the macrocell feedback and the corresponding I/O feedback to be available for each programmable logic block. This rotation allows the buried register capability without increasing the array size and is one of the important features of this invention.

FIGS. 53A to 56D illustrate the actual switch matrix signal patterns for all eight programmable logic blocks 402B3 of PLD 230. The columns in FIGS. 53A to 56D are the signals in the band which are rotated within the column, as described above, and each row is the input signals to a 16 to 1 multiplexer that provides the input signal on the input line indicated in the left hand column. Note, for ease of representation FIGS. 53A to 56D include the input line column in each figure.

However, only a single input signal is provided by each row of the table shown in the four figures representing one portion of switch matrix 402B3.

In particular, FIG. 53A to FIG. 53D represent the portions of the switch matrix that drive programmable logic block 402B3-1 and 402B3-8. FIG. 54A to FIG. 54D represent the portions of the switch matrix that drive programmable logic blocks 402B3-2 and 402B3-7. FIG. 55A to FIG. 55D represent the portions of the switch matrix that drive programmable logic blocks 402B3-3 and 402B3-6. FIG. 56A to FIG. 56D represent the portions of the switch matrix that drive programmable logic blocks 402B3-4 and 402B3-5.

Switch matrix 401B3 for PLD 230 provides eight sets of 26 input lines--one set for each PLB 402B3. Each of these 26 input lines are derived from a 16:1 multiplexer set. The 26 input signals can be unique or the same for each PLB 402B3. This allows device 230 to function as a monolithic array with a maximum of 26 inputs out of the 134 or eight separate, relatively independent split-arrays with a total maximum number of inputs of 198 (out of possible 198), or alternatively 4 pairs of devices. Thus, as described above, programmable logic devices 110, 120, 130, 210, 220, and 230 of this invention have a plurality of programmable connections. The programmable connections are controlled by a multiplicity of electrically erasable cells. The number of cells depend upon the specific implementation, but the number of cells for each device are given in Tables 8 to 13 respectively. The number of cells are illustrative of the embodiments described above. In view of this disclosure, one skilled in the art can design PLDs according to the principles of this invention with differing numbers of erasable cells. Accordingly, the following Tables are illustrations only and are not intended to limit the invention to the number of cells indicated.

                  TABLE 8                                                          ______________________________________                                         Device 110                                                                     ______________________________________                                         E.sup.2 cells for the                                                                              2 × 44 × 70 =                                                                  6,160                                          AND-OR array                                                                   E.sup.2 cells for the programmable                                                                 2 × 16 × 4 =                                                                     128                                          logic macrocells                                                               E.sup.2 cells for the programmable                                                                 2 × 2 × 16 =                                                                     64                                           input/output macrocells                                                        E.sup.2 cells for the                                                                              2 × 2 × 16 =                                                                     64                                           logic allocator                                                                E.sup.2 cells for the                                                                              2 × 3 × 4 =                                                                      24                                           switch matrix       2 × 2 × 16 =                                                                     64                                           TOTAL                           6,504                                          ______________________________________                                    

                  TABLE 9                                                          ______________________________________                                         Device 120                                                                     ______________________________________                                         E.sup.2 cells for the                                                                              4 × 52 × 54 =                                                                  11,232                                         AND-OR array                                                                   E.sup.2 cells for the programmable                                                                 4 × 12 × 5 =                                                                     240                                          logic macrocells                                                               E.sup.2 cells for the programmable                                                                 4 × 2 × 12 =                                                                      96                                          input/output macrocells                                                        E.sup.2 cells for the                                                                              4 × 2 × 12 =                                                                      96                                          logic allocator                                                                E.sup.2 cells for the                                                                              4 × 4 × 26 =                                                                     416                                          switch matrix                                                                  TOTAL                           12,080                                         ______________________________________                                    

                  TABLE 10                                                         ______________________________________                                         Device 130                                                                     ______________________________________                                         E.sup.2 cells for the                                                                              2 × 52 × 70 =                                                                  14,560                                         AND-OR array                                                                   E.sup.2 cells for the programmable                                                                 4 × 16 × 5 =                                                                     320                                          logic macrocells                                                               E.sup.2 cells for the programmable                                                                 4 × 2 × 16 =                                                                     128                                          input/output macrocells                                                        E.sup.2 cells for the                                                                              4 × 2 × 16 =                                                                     128                                          logic allocator                                                                E.sup.2 cells for the                                                                              4 × 4 × 26 =                                                                     416                                          switch matrix                                                                  TOTAL                           15,552                                         ______________________________________                                    

                  TABLE 11                                                         ______________________________________                                         Device 210                                                                     ______________________________________                                         E.sup.2 cells for the                                                                              4 × 44 × 68 =                                                                  11,968                                         AND-OR array                                                                   E.sup.2 cells for the programmable                                                                 4 × 16 × 4 =                                                                     256                                          logic macrocells                                                               E.sup.2 cells for the programmable                                                                 4 × 2 × 8 =                                                                       64                                          input/output macrocells                                                        E.sup.2 cells for the                                                                              4 × 2 × 16 =                                                                     128                                          logic allocator                                                                E.sup.2 cells for the                                                                              4 × 4 × 22 =                                                                     352                                          switch matrix                                                                  TOTAL                           12,704                                         ______________________________________                                    

                  TABLE 12                                                         ______________________________________                                         Device 220                                                                     ______________________________________                                         E.sup.2 cells for the                                                                              8 × 52 × 52 =                                                                  21,632                                         AND-OR array                                                                   E.sup.2 cells for the programmable                                                                 8 × 12 × 5 =                                                                     480                                          logic macrocells                                                               E.sup.2 cells for the programmable                                                                 8 × 2 × 6 =                                                                       96                                          input/output macrocells                                                        E.sup.2 cells for the                                                                              8 × 2 × 12 =                                                                     192                                          logic allocator                                                                E.sup.2 cells for the                                                                              8 × 4 × 26 =                                                                     832                                          switch matrix                                                                  TOTAL                           23,232                                         ______________________________________                                    

                  TABLE 13                                                         ______________________________________                                         Device 230                                                                     ______________________________________                                         E.sup.2 cells for the                                                                              8 × 52 × 68 =                                                                  28,288                                         AND-OR array                                                                   E.sup.2 cells for the programmable                                                                 8 × 16 × 5 =                                                                     640                                          logic macrocells                                                               E.sup.2 cells for the programmable                                                                 8 × 2 × 8 =                                                                      128                                          input/output macrocells                                                        E.sup.2 cells for the                                                                              8 × 2 × 16 =                                                                     256                                          logic allocator                                                                E.sup.2 cells for the                                                                              4 × 8 × 26 =                                                                     832                                          switch matrix                                                                  TOTAL                           30,144                                         ______________________________________                                    

In the preceding discussion, for ease of expression, only programmable architectural cells have been described. The cells in these applications may be fuses, EPROM cells, EEPROM cells, RAM cells, or CMOS antifuse technology in accordance with the invention. The architectural cells are a means for providing either an input select signal or an output select signal to a programmable component so that the component passes a desired signal therethrough.

The preceding discussion has described a programmable AND/OR array as an assembly of AND gates used to form products of logical variables, followed by an assembly of OR gates to form sums of such product terms. However, using logical transforms known to those skilled in the art, in a preferred embodiment the programmable AND, fixed OR array (AND/OR array) is replaced by a programmable NOR, fixed NOR array. The use of NOR logic provides enhanced speed over the equivalent programmable AND/OR array, but the logic functions of the two arrays are equivalent.

The AND/OR array also may include inverters that form complements (A) of the input signals (A). The AND/OR array may also be arranged as an assembly of OR gates to form sums of logical variables, followed by an assembly of AND gates to form products of such sums, by utilizing the DeMorgan theorems

    A·B=A+B,

    A+B=A·B

in a manner well known to those of ordinary skill in the art. For example, the sum of logical product terms A·B+C·D+E·F·G may be written as the complement of the product of sums of complemented variables, viz

    A·B+C·D+E·F·G=(A+B)·(C+D).multidot.(E+F+G)

For ease of reference, a logical sum of logical products and a logical product of logical sums are collectively referred to herein as "logical sum/product terms."

The gate configuration illustrated in FIGS. 17A to 18D for example is expressed in the PAL mode, where the AND gates are normally programmable and the OR gates are normally fixed. Using the DeMorgan theorems applied above and incorporating signal inverters in the signal paths, one can also express the gate configuration in terms of programmable OR gates and fixed AND gates. More generally, one may configure the gates in a PLA mode, wherein both AND gates and OR gates are programmable.

The switching characteristics of the programmable logic device 400 of this invention are given in Tables 14 and 15 and the DC characteristics in Table 16. The parameter symbols and parameters definitions are described more completely in PAL Device Data Book, Advanced Micro Devices, Sunnyvale, Calif., pp. 5-533 to 5-535 (1988), which are incorporated herein by reference. The characteristics in Tables 14-16 are illustrative of one embodiment of this invention are not intended to limit this invention to the specific values disclosed.

                  TABLE 14                                                         ______________________________________                                         AC Characteristics of PLDs 110, 120 and                                        130 of this Invention                                                          Para-                                                                          meter  Parameter      (-15)     (-20)                                          Symbol Description    Min    Max  Min  Max  Units                              ______________________________________                                         COMBINATORIAL/REGISTERED OPERATION                                             t.sub.PD                                                                              Input or I/O          15        20   ns                                        to Combinatorial                                                               Output                                                                  Output Register                                                                t.sub.SU                                                                              Input or IO    10          13        ns                                        Pin to Output                                                                  Register                                                                       D-FF Setup     12          15        ns                                 t.sub.CO                                                                              Clock to output       10        12   ns                                 t.sub.COF                                                                             Clock to feedback      6         8   ns                                 t.sub.HOR                                                                             Data Hold Time 0           0         ns                                        for Output                                                                     Register                                                                Clocking and Frequency                                                         t.sub.CIS                                                                             Register Feedback                                                                             16          20        ns                                        to Output Register                                                             latch Setup                                                             f.sub.MAXO                                                                            MAX External                                                                   Frequency                                                                      1/(t.sub.SU + t.sub.CO)                                                        D-type         50          40        MHz                                       T-type         45.5        37        MHz                                f.sub.MAXI                                                                            MAX Internal                                                                   Frequency                                                                      1/(t.sub.CIS)                                                                  D-type         62.5        50        MHz                                       T-type         55.5        43.5      MHz                                t.sub.CWH                                                                             Clock Width High       6         8   ns                                 t.sub.CWL                                                                             Clock Width Low        6         8   ns                                 f.sub.MAX                                                                             MAX Clock      83.3        62.5      MHz                                       Frequency                                                               RESET/PRESET & OUTPUT ENABLE OPERATION                                         t.sub.APO                                                                             Input or I/O          20        25   ns                                        Pin to Output                                                                  Register/Latch                                                                 RESET/PRESET                                                            t.sub.ARO                                                                             Async. RESET/  20          25        ns                                        PRESET to Output                                                               Register/Latch                                                                 Recovery                                                                t.sub.ARI                                                                             Async. RESET/  10          15        ns                                        PRESET to Input                                                                Register/Latch                                                                 recovery                                                                t.sub.AW                                                                              Aysync. RESET/ 15          20        ns                                        PRESET Pulse                                                                   Width                                                                   t.sub.EA                                                                              Output Buffer         15        20   ns                                        Enable                                                                  t.sub.ER                                                                              Output Buffer         15        20   ns                                        Disable                                                                 ______________________________________                                    

                  TABLE 15                                                         ______________________________________                                         AC Characteristics of PLDs 210, 220 and                                        230 of this Invention                                                          Para-                                                                          meter  Parameter      (-15)     (-20)                                          Symbol Description    Min    Max  Min  Max  Units                              ______________________________________                                         COMBINATORIAL/REGISTERED OPERATION                                             t.sub.PD                                                                              Input or I/O Pin      15        20   ns                                        to Combinatorial                                                               Output                                                                  Output Register                                                                t.sub.SU                                                                              Input or IO    10          13        ns                                        Pin to Output                                                                  Register                                                                       D-FF Setup                                                                     T-FF Setup     12          15        ns                                 t.sub.CO                                                                              Clock to output       10        12   ns                                 t.sub.COF                                                                             Clock to feedback      6         8   ns                                 t.sub.HOR                                                                             Data Hold Time 0           0         ns                                        for Output                                                                     Register                                                                Input Register                                                                 t.sub.SIRD                                                                            Input or I/O   4           5         ns                                        Pin to Input                                                                   Register D-FF                                                                  Setup                                                                   t.sub.CIR                                                                             Register Feedback     20        30   ns                                        Clock to                                                                       Combinatorial Output                                                    t.sub.HIR                                                                             Data Hold Time 4           5         ns                                        for Input Register                                                      Clocking and Frequency                                                         t.sub.CIS                                                                             Register Feedback                                                                             16          20        ns                                        to Output Register                                                             latch Setup                                                             f.sub.MAXO                                                                            MAX External                                                                   Frequency                                                                      1/(t.sub.SU + t.sub.CO)                                                        D-type         50          40        MHz                                       T-type         45.5        37        MHz                                f.sub.MAXI                                                                            MAX Internal                                                                   Frequency                                                                      1/(t.sub.CIS)                                                                  D-type         62.5        50        MHz                                       T-type         55.5        43.5      MHz                                t.sub.CWH                                                                             Clock Width High       6         8   ns                                 t.sub.CWL                                                                             Clock Width Low        6         8   ns                                 f.sub.MAX                                                                             MAX Clock      83.3        62.5      MHz                                       Frequency                                                               LATCH OPERATION                                                                t.sub.PD                                                                              Input or I/O Pin      15        20   ns                                        to Combinatorial                                                               Output                                                                  t.sub.PTD                                                                             Input or I/O Pin      20        25   ns                                        to Output via                                                                  One Transparent                                                                Latch                                                                   Output Latch                                                                   t.sub.SOL                                                                             Input or I/O Pin      10        13   ns                                        to Output Latch                                                                Setup                                                                   t.sub.GOL                                                                             Latch Enable to       10        12   ns                                        Transparent Mode                                                               Output                                                                  t.sub.HOL                                                                             Data Hold time for                                                             Output Latch   0           0         ns                                 Input Latch                                                                    t.sub.SIL                                                                             I/O Pin to Input                                                                              4           5         ns                                        Latch setup                                                             t.sub.GIL                                                                             Latch Feedback,       20        25   ns                                        Latch Enable                                                                   Transparent Mode                                                               to Combinatorial                                                               Output                                                                  t.sub.HIL                                                                             Data Hold Time for                                                                            4           5         ns                                        Input Latch                                                             Latch Enable                                                                   t.sub.GIS                                                                             Latch Feedback 20          25        ns                                        Transparent Mode to                                                            Output Register/                                                               Latch setup                                                             t.sub.GWH                                                                             Latch Enable   8           10        ns                                        Width High                                                              t.sub.GWL                                                                             Latch Enable   8           10        ns                                        Width Low                                                               RESET/PRESET & OUTPUT ENABLE OPERATION                                         t.sub.APO                                                                             Input or I/O          20        25   ns                                        Pin to Output                                                                  Register/Latch                                                                 RESET/PRESET                                                            t.sub.ARO                                                                             Async. RESET/  20          25        ns                                        PRESET to Output                                                               Register/Latch                                                                 Recovery                                                                t.sub.ARI                                                                             Async. RESET/  10          15        ns                                        PRESET to Input                                                                Register/Latch                                                                 recovery                                                                t.sub.AW                                                                              Aysync. RESET/ 15          20        ns                                        PRESET Pulse                                                                   Width                                                                   t.sub.EA                                                                              Output Buffer         15        20   ns                                        Enable                                                                  t.sub.ER                                                                              Output Buffer         15        20   ns                                        Disable                                                                 ______________________________________                                    

                                      TABLE 16                                     __________________________________________________________________________     DC Characteristics of All PLDs of this Invention                                                TEST                                                          PARAMETER                                                                              DESCRIPTION                                                                             CONDITIONS   MIN                                                                               TYP                                                                               MAX   UNITS                                __________________________________________________________________________     V.sub.CC                      4.75  5.25  Volts                                V.sub.OH                                                                               Output   Vcc = Min    2.4                                                                               3.5      Volts                                        HIGH     Vin = V.sub.IH or V.sub.IL                                            Voltage  I.sub.OH = -3.2 mA COM'l                                                       I.sub.OH = -2 mA MIL                                          V.sub.OL                                                                               Output   Vcc = Min          0.5   Volts                                        LOW      Vin = V.sub.IH or V.sub.IL                                            Voltage  I.sub.OL = 16 mA COM'L                                                         I.sub.OL = 12 mA MIL                                          V.sub.IH                                                                               Input    Guaranteed Logic   2.0   Volts                                        HIGH     HIGH for all                                                                   Input Pins Voltage                                            V.sub.IL                                                                               Input    Guaranteed Logic   0.8   Volts                                        LOW      LOW for all input pins                                                Voltage                                                                I.sub.I Input    Vin = 0 to 5.5 V   10    uA                                           Leakage  Vcc = Max                                                             Current                                                                I.sub.O Output   Vin = 0 to 5.5 V   10    uA                                           Leakage  Vcc = MAX                                                             Current                                                                I.sub.CCOP                                                                             DC Current                                                                              Outputs Open       200   mA                                           Supply   (lo = 0), F = 0 MHz                                           I.sub.SC                                                                               DC short VCC = MAX, Vo = 5 V                                                                               -130  mA                                           Circuit                                                                        Current                                                                CAPACITANCE                                                                    CIN     Input    Vcc = 5 V,   9           pF                                           Capac-   TA = 25 deg. C.                                                       itance   Vin = 2 V                                                     COUT    Output   Vout = 2 V @ 11          pF                                           Capac-   f = 1 MHZ                                                             itance                                                                 __________________________________________________________________________

The parameter f_(MAX) is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, parameter f_(MAX) is specified for three types of synchronous designs.

The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device input pins, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (t_(SU) +t_(CO)). The reciprocal, f_(MAX), is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This f_(MAX) is designated "f_(MAXO) ".

The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs (t_(CIS)). This f_(MAX) is designated "f_(MAXI) ".

The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold (t_(SU) +t_(HOR)). However, a lower limit for the period of each f_(MAX) type is the minimum clock period (t_(CWH) +t_(CWL)). Usually, this minimum clock period determines the period for the third f_(MAX), designated "f_(MAX) ".

The family of programmable logic devices 400 supports 50 MHz system clocks of the emerging high speed RISC and CISC microprocessor applications. As described above, the external f_(MAX) for family 400 is 50 MHz. This 50 MHz frequency includes the clock to external pin delay time and the setup time of the flip-flop. Hence, a state machine can be implemented in device 400 running at a 50 MHz system clock frequency. Data signals can be sent off chip for communicating either to a second device or possibly externally feeding back to device 400 at 50 MHz clock rate.

In addition to supporting the 50 MHz external clock frequency in this embodiment, the family of devices 400 supports internal clock frequencies of 62.5 MHz and pipelined frequency of up to 83 MHz.

Fundamentally, the architecture of this invention has two simple time delay parameters, i.e., array delay and switch matrix delay. The input-to-output pin-to-pin delay for a single programmable logic block 402, including switch matrix 401 and programmable array time delays is about 15 ns for the worst case (including temperature, voltage). For signals traversing through multiple programmable logic blocks externally, the delay time is simple multiples of 15 ns. For example, the time delay for a signal traversing through two programmable logic blocks via switch matrix 401 is about 30 ns, three blocks time delay is about 45 ns. Delay computations for the devices of this invention are simple, fast, predictable and are internal path independent. This is unlike some of the complex, mid-density PLDs, where the delays are slow, variable, internal path dependent, and fairly tedious to compute. The family of devices 400 maintains the inherent simplicity and fixed time predictability of traditional PAL devices--offering designers fairly simple, predictable performance, prior to implementing designs.

The high performance architecture of devices 400 supports both gate intensive and register intensive functions at high speed. For example, 16-bit address decoder, 16-bit multiplexer or 4 to 16 demultiplexers (gate intensive functions) or 16-bit loadable up-down counters and 16-bit binary synchronous counters (register intensive functions) can be implemented at a maximum frequency of 50 MHz, enabling device 400 to be operated with up to 50 MHz RISC and CISC microprocessors.

Further, programmable logic block 402 structure with a high speed switch matrix 401 supports extremely logic intensive logic functions via two levels of fixed worst case time delays of 30 ns. In a programmable logic device 400 having four programmable logic blocks 402, such as device 400B, more than 192 product term logic functions can be incorporated with 30 ns time delays.

The simple programmable architecture of this invention requires simple, easy to use software for programming the device and obviates the need for an expensive, complex software package.

User designs for device 400 are entered via a variety of design entry mechanisms, for example, Boolean equation and State machines. Signals that need to be located on critical pins can be specified by the user. A software fitting means automatically allocates the resources of programmable logic device 400 to each of the logic equations in the user design.

As a result of the advanced synthesis and optimization techniques of the fitting means, designs are configured to architecture of this invention in minutes. The fitting means has intelligence and knowledge about optimal block partitioning (fitting user logic equations in a single programmable logic block) and routing signals to appropriate blocks via the switch matrix without any manual intervention. Hence, the designers do not have to worry about any manual routing or fitting of logic.

The software generates a JEDEC file for programming device 400. Device 400 can be programmed on conventional, industry standard PAL programmers with appropriate personality and socket adapter modules. One embodiment of the fitting means is described in copending, commonly filed, and commonly assigned U.S. patent application Ser. No. 07/490,817 entitled "An Apparatus and Method for Allocation of Resources in Programmable Logic Devices" of N. Schmitz, which is incorporated herein by reference in its entirety.

All programmable logic macrocells 412 have been designed to be reset during power-up. Following the power-up, all programmable logic macrocells 412 are cleared, setting the output signals to a logical zero. This feature is especially valuable in simplifying state machine initialization.

A security cell is provided on each device to prevent unauthorized copying of the user's proprietary logic design. Once programmed, the security cell disables the programming and verification modes. The only way to erase the protection cell is y charging the entire array architecture cells. This cell should preferably be programmed only after the rest of the device has been completely programmed.

Programmable logic device 400 is designed with supervoltage enabled preload circuitry that provides an easy method for testing the logic functionality.

The preload function allows any arbitrary state value to be loaded into macrocells 412. A typical functional test sequence would be to verify all possible state transitions for the device being tested. This requires the ability to set the state registers into an arbitrary "present state" and to set the device into an arbitrary "present input" value. Once this is done, the state machine is clocked into a new state, or next state which can be checked to validate the transition from the "present state". In this way, any particular state transition can be checked.

Since the preload function allows the device to go directly into any desired state, test sequences may be greatly shortened. Also, all possible values can be tested, thus greatly reducing both test time and development costs and guaranteeing proper in-system operation.

An observability mode allows the ability to observe the contents of internal state or output registers on corresponding I/O pins for testability. This observability mode is entered by applying a supervoltage to certain pins. Once this mode is entered, it suppresses the combinatorial output data from appearing on the I/O pins and allows the observation of the contents of output registers on the output pins corresponding to the programmable logic macrocells. This allows easy debugging and tracing of the buried registers.

While the present invention has been described in terms of an embodiment having programmable multiplexers with a specific number of input lines and a specific number of architectural configuration cells, these embodiments are illustrative only and not intended to limit the scope of the invention. Following the principles of this invention, one skilled in the art could implement various configurations of lines to the multiplexers and add or subtract configuration cells as previously described to achieve a flexibility not present in the prior art programmable devices.

Moreover, PLDs 400 were described in terms of synchronous applications. However, asynchronous PLD 215 of this invention can be derived from the basic core of PLD 210. Specifically, in one embodiment of the family of PLDs of this invention, each family includes asynchronous PLDs as well as synchronous PLDs. The structure of the asynchronous PLDs of this family are configured to support the requirements of asynchronous logic.

Generally, synchronous sequential logic applications require PLDs with (i) a number of registers, anywhere from 4 to less than 64 for applications of small to medium complexity and greater than 64 for more complex applications, (ii) preferably some buried registers that are not tied to I/O pins, (iii) a number of product terms, preferably 4 to 16, per macrocell, (iv) user-programmable I/O macrocells, (v) programmable polarity control, (vi) AND-OR logic capability, (vii) a flexible common clocking scheme, and (viii) reset and preset control mechanisms for storage registers as well as preload and observability capability for hidden state register bits.

In contrast, asynchronous logic applications require PLDs with registers having individual reset/preset capability, individual clock with polarity control, individual output enable control, and fewer product terms per macrocell. Typically, in synchronous logic applications, registers are grouped, often as banks of registers, and associated I/O pins are controlled on a group basis (nibble, byte or word), whereas for asynchronous logic applications, individual control for each programmable storage element is essential.

According to the principles of this invention, an asynchronous programmable logic device is derived from the core of a synchronous programmable logic device, described more completely above. Since the asynchronous PLDs of this invention are derived from the synchronous PLDs described above, the asynchronous PLDs include the same basic architecture and advantages in routability of signals and scaling that were described above for the synchronous PLDs. Specifically, each asynchronous programmable logic block is identical. The asynchronous programmable logic blocks are interconnected by the novel centralized high speed switch matrix, described above. Thus, every signal passed through the switch matrix, irrespective of the signal's origin, encounters the same high speed, fixed, uniform, predictable, and path independent time delay through the switch matrix. Preferably, the programmable logic blocks are symmetric about the switch matrix as illustrated in FIG. 9.

In one embodiment, each asynchronous programmable logic block includes dedicated output logic macrocells, dedicated input logic macrocells and dedicated I/O cells, all of which are described more completely below. Since the basic function of the asynchronous programmable logic blocks is the same as the programmable logic blocks described above, only the changes necessary to that basic function to derive the asynchronous PLDs of this invention are described below.

FIGS. 57A and 57B illustrate one embodiment of 44-pin asynchronous programmable logic device 215 which has 32 I/O pins 403B4-1 to 403B4-32 and six dedicated direct input pins 404B4-1 to 404B4-6. Each of asynchronous programmable logic blocks 402B4-1 to 402B4-4 is identical and each includes a programmable product array, preferably a 44×64 product term array 410B4-1 to 410B4-4, a programmable logic allocator 411B4-1 to 411B1-4, eight asynchronous programmable logic macrocells 412B4-1 to 412B4-4. Each programmable logic block also includes eight input logic macrocells 415B4-1 to 415B4-4.

In one embodiment of this invention, asynchronous PLD 215 is a general purpose, high performance, high density, asynchronous programmable logic device that is derived from the core of synchronous PLD 210. PLD 215 is a first asynchronous PLD which complements the synchronous logic family of PLDs 110, 120, 130, 210, 220 and 230. The combination of synchronous and asynchronous PLDs within the family permits the family to address a broader range of random TTL logic replacement applications than a family of only synchronous PLDs. Further, derivation of the asynchronous PLDs from the synchronous PLDs reduces production costs and facilitates migration of designs between the various synchronous and asynchronous PLDs.

PLD 215 includes a large number of flexible asynchronous output logic macrocells 412B4, as described more clearly below, and is designed to replace arbitrary TTL replacement logic in small PAL devices. The 1200 to 1500 equivalent data density of PLD 215 offers approximately three times the logic macrocell capability of the industry standard PLD PAL20RA10, two times the logic macrocell capability of the PLD EP610 and two times the logic macrocell capability of PLD 29MA16 with speed performance comparable to these lower density PLDs and with a lower cost per macrocell.

Recall, as described above, PLD 210 (FIGS. 14A and 14B) has two programmable storage elements 412BA1, 412BB1 associated with each I/O pin 403B1. One programmable storage element is used as an output logic macrocell 412BA1 and the other programmable storage element is used for a buried/input logic macrocell 412BB1. Product term array 410B1 (FIGS. 18A through 18D) had four product terms for each macrocell in the programmable logic block, i.e., a total of 64 logic product items.

In PLD 215 (FIGS. 57A and 57B), the four product terms associated with buried/input logic macrocell 412BB1 of PLD 210 (FIGS. 14A and 14B) are used for individual reset, individual preset, individual clock signal for the asynchronous logic output macrocell 412B4 and individual output enable control for an I/O macrocell 413B4 (FIGS. 57A and 57B). Buried macrocell 412BB1 of PLD 210 is utilized as input logic macrocell 415B4 of PLD 215 to provide register/latch input capability. The other aspects of PLD 215 are substantially identical to those in PLD 210. However, as explained more completely below, logic allocator 411B4 is a simplication of logic allocator 411B1 of PLD 210. The simplification obtains better speed performance for PLD 215.

Switch matrix 401B4 is identical to switch matrix 401B1 (FIGS. 42 through 44C), described more completely above, and provides 22 input signals to product term array 410B4 (FIG. 57A) over 22 input lines 426B4. As described above for the synchronous PLDs, the asynchronous PLDs of this invention receive input signals only from switch matrix 401B4 over asynchronous programmable logic block input lines 426B4.

Asynchronous programmable logic macrocells 412B4 provide eight feedback signals to switch matrix 401B4 over eight lines in lines 427B4. Input logic macrocells 415B4 provide another eight signals to switch matrix 401B4 over another eight lines in lines 427B4. I/O macrocells 413B1 provide I/O-pin 403B4 signals to switch matrix 401B4 over eight lines 428B4. In FIGS. 57A and 58B, two dedicated input pins 404B4-1, 404B4-4 are either a dedicated input pin, a dedicated clock pin or a clock/input pin. Pins 404B4-1, 404B4-4 are coupled to switch matrix 401B1 and to programmable logic macrocells 412B4. In another embodiment, pins 401B4-2, 404B4-4 may also be coupled to input logic macrocells 415B4.

Programmable product term array 410B4 in PLD 215 is the same as product term array 410B1 of PLD 210 (FIGS. 18A through 18D), but four product terms of array 410B1 are left unused, i.e., common asynchronous reset product term 410B1-i-67, common asynchronous preset product term 41OB1-i-68 and two common output enable product terms 410B1-i-65 and 410B1-i-66 are not utilized in PLD 215. Thus, PLD 215 has a total of 256 product terms, i.e., 64 product terms for each programmable logic block 402B4. In each programmable logic block 402B4, the 64 product terms consist of 32 logic product terms and 32 control product terms in this embodiment.

As described above for the synchronous family of programmable logic devices, one of the main reasons for programmable logic structures silicon inefficiency has been fixed product term allocation for each macrocell. Most of the industry-standard programmable logic devices have a fixed overhead of eight or more product terms and less than a single control product term for each output logic macrocell to handle a range of functions. While a fixed allocation of product terms allows flexibility, this structure results in wasted valuable resources. Product terms remain unused if the application requires less than the fixed allocated resource.

Programmable logic block 402B4 of this invention includes logic allocator 411B4 that allocates the 32 logic product terms among asynchronous output logic macrocells 412B4. The 32 logic product terms in each programmable logic block 402B4 of PLD 215 are distributed among eight asynchronous output logic macrocells 412B4 in that block as described more completely below. A fixed number of control product terms are provided to each asynchronous output logic macrocell 412B4-i-n. (Here "i" represents one of the programmable logic blocks and "n" represents an output logic macrocell within that block.) In one embodiment, these control product terms include an individual asynchronous reset, an individual asynchronous preset, an individual clock product term. An individual output enable product term is provided to each I/O macrocell 413B4-i-n. These four product terms were logic product terms that were associated with a buried macrocell in synchronous PLD 210.

Logic allocator 411B4 includes eight router elements 520B4 (FIG. 58). Each router element 520B4 includes OR gate 521B4, which is driven by signals from four product term lines of product term array 410B4, and a programmable one-to-three demultiplexer 522B4 which has a single input terminal and three output terminals. Architectural configuration cells 523B4, 524B4 are used to form a connection between the input terminal and only one of the output terminals. Cells 523B4, 524B4 provide an output select signal to demultiplexer 522B4 so that the signal on the input line is passed therethrough to the selected output line. In this embodiment, OR gate 521B4 is included within router element 520B4, but alternatively the OR gate could be included with the product term array so that a programmable AND-OR array generated signals for logic allocator 411B4.

In the PLD 215, two router elements 520B4-1 (FIG. 59A), 520B4-8 (FIG. 59C) of logic allocator 411B4 may provide a signal to only two asynchronous logic macrocells, e.g. router element 520B4-1 drives either logic macrocell 412B4-i-1 or logic macrocell 412B4-i-2 and router element 520B4-8 drives either logic macrocell 412B4-i-8 or logic macrocell 412B4-i-7. Each of the other six router elements 520B4-i-n (FIG. 59B) in logic allocator 411B4 may provide a signal to macrocell 412B4-i-(n-1) or to macrocell 412B4-i-n or to macrocell 412B4-i-(n+1) where n equals 2, 3 . . . , 7. The configuration of router elements for asynchronous PLD 215 described herein is illustrative only of a plurality of router elements with each router element steering a fixed number of product terms to a selected output logic macrocell. This description is not intended to limit the invention to this specific configuration described.

Thus, in this embodiment, asynchronous logic macrocells 412B4-i-2 through 412B4-i-7 may receive up to a maximum of a sum of 12 product terms while logic macrocells 412B4-i-1 and 412B4-i-8 may received up to a maximum of a sum of only eight product terms. Of course, in another embodiment, logic allocator 411B4 could be configured to provide up to a sum of sixteen product terms. As in the synchronous PLDs of this invention, complete wraparound is not supported by logic allocator 411B4. Complete wraparound is estimated to cause a degradation in speed performance of about 1 to 2 nanoseconds for signal propagation from an input pin through programmable logic device 215 to an output pin.

The operation of logic allocator 411B4 is illustrated in FIG. 60. Boxes L1, L3, L5 . . . L15 on the left-hand side of the figure, represent the product terms in array 410B4. Each box has either four logic product terms or four control product terms. On the right-hand side of FIG. 60 are 16 boxes R1 through R16. The odd-numbered boxes represent asynchronous output logic macrocells 412B4-i-1 to 412B4-i-8 respectively. The even-numbered boxes on the right-hand side of the figure represent input logic macrocells 415B4-i-1 to 415B4-i-8 respectively and as shown the input logic macrocells do not receive any logic product terms from the product term array.

As in the synchronous PLDs of this invention, asynchronous PLD 215 does not have any logic product term resources permanently allocated to a specific asynchronous macrocell by logic allocator 411B4. Accordingly, if an I/O pin that is coupled to an asynchronous macrocell for example, the macrocell labeled R9 in FIG. 60, is used as an input pin and the buried register capability of macrocell R9 is not needed, the product terms from cells L7, L9, and L11 may be utilized by other macrocells. Thus, there are no wasted logic product terms associated with logic macrocell R9, when the macrocell is not utilized.

The operation of the one-to-three demultiplexer is equivalent to the operation of the demultiplexers in the logic allocators of the synchronous programmable logic devices described above, and that description is incorporated herein by reference. Thus, according to principles of this invention, the numbers of sums of logical product terms for each asynchronous logic macrocell 412B4 from programmable logic block 402B4 are variable and may range from a sum of four product terms to three sums of four product terms, i.e., 12 product terms for each logic macrocell, in one embodiment.

Each asynchronous logic macrocell 412B4 (FIG. 61) in PLD 215 is identical so that asynchronous logic output macrocell 412B4 is representative of any logic macrocell in this embodiment of PLD 215. In asynchronous logic macrocell 412B4, a plurality of logic terms from logic allocator 411B4 are supplied on the n-input lines to OR gate 500. The output line of OR gate 500 is connected to the input terminal of a programmable element 503A.

Programmable element 503A may be configured to have either an output signal from any one of a D-type flip-flop, a T-type flip-flop, and a transparent latch, or a combinatorial signal. (See FIG. 29A and FIG. 29B which are incorporated herein by reference.) Architectural cells 504 and 506 are used to configure programmable element 503A so that the desired type of output signal is on the output terminal of element 503A. The operation of programmable element 503A is the same as that described above for the synchronous PLDs because, as previously described, the same core is used for both asynchronous and synchronous PLDs. Accordingly, the above description of the programmable storage element is incorporated herein by reference. Of course, the other storage elements that were described above for the synchronous PLDs of this invention could also be incorporated in asynchronous PLD 215.

One control product term is connected to the asynchronous preset terminal AP of element 503A and another control product term is connected to the asynchronous reset terminal AR. A third control product term, that functions as a clock product term, drives one input terminal of four-to-one clock multiplexer 501 which has architectural configuration cells 502A and 502B. The signal on the clock product term line also drives an inverting terminal of multiplexer 501 so that the signal on the clock product term line effectively provides both a rising edge signal and a falling edge signal. Similarly, a signal on dedicated input pin 404B-1 drives another input terminal of clock multiplexer 501 and another inverting terminal of multiplexer 501. The signal on the output terminal of multiplexer 501 drives the clock terminal of programmable element 503A.

The output terminal of programmable element 503A is connected to the switch matrix as well as to a first input terminal of a two-to-one polarity control multiplexer 507. Since a feedback signal is provided to the switch matrix for either a registered, latched, or combinatorial output signal, output logic macrocell 412B4 allows for buried sequential or combinatorial functions freeing up the I/O pin for use as an input pin.

The output terminal of programmable element 503A is also connected to an inverting terminal of multiplexer 507. As previously described, for output logic macrocell 412A2 in PLD 120, multiplexer 507 is an output polarity control multiplexer. The output signal from the polarity control multiplexer 507 drives an I/O macrocell. The programming of programmable element 503A, polarity control multiplexer 507, and clock multiplexer 501 is shown schematically within the multiplexers in FIG. 61 and is equivalent to the description above for the synchronous PLDs of this invention, which is incorporated herein by reference.

Thus, an asynchronous logic output macrocell 412B4, according to this invention, may be configured so that the output signals are either registered, latched or combinatorial with an active high or an active low polarity. When the asynchronous logic macrocell is used as a register, the logic macrocell can further be configured as a D-type or a T-type flip-flop. Alternatively, element 503A can provide a latched signal or a combinatorial signal.

Recall that the buried macrocells of the synchronous PLDs, as described above, are utilized as input logic macrocells 415B4 in asynchronous PLD 215. However, only the four-to-one clock multiplexer 501, the D-type flip-flop and the latch capability of the programmable element are utilized in this embodiment. Specifically, as shown in FIG. 62, the signal from an I/O pin drives the input terminal of programmable storage element 503C, which is configurable either as a D-type flip-flop or a latch by architectural cell 506. The clock input terminal of storage element 503C is driven by the output signal from four-to-one clock multiplexer 501. A signal on dedicated input pin 404B4-1 drives one input terminal and one inverting input terminal of multiplexer 501 in input logic macrocell 415B4. A signal on dedicated input pin 404B4-4 drives the other input terminal and the other invention terminal of multiplexer 501. In another embodiment (not shown), the input terminal connections of clock multiplexer 501 are identical to those described above for the input terminals of clock multiplexer in the output logic macrocells and that description is incorporated herein by reference.

The output signal from programmable storage element 503C is provided only to switch matrix 401B4. This feedback signal is always provided from programmable storage element 503C and is always available irrespective of the I/O macrocell configuration.

Both asynchronous output logic macrocell 412B4 and input logic macrocell 415B4 of PLD 215 are clocked by one of four clock sources on an individual macrocell basis. As illustrated in FIG. 61, these four clock sources for asynchronous logic macrocell 412B4 are: one from a first synchronous clock input pin rising edge, one from the first synchronous clock input pin trailing edge, one from the clock product term rising edge derived from the programmable product term array and one from the clock product term trailing edge derived from the programmable product term array. This allows up to a maximum of 32 clocks, one separate clock for each storage element.

As illustrated in FIG. 62, the four clock sources for input logic macrocell 415B4 are: one from a first synchronous clock input pin rising edge, one from the first synchronous clock input pin trailing edge, one from a second synchronous clock input pin rising edge and one from the second synchronous clock input trailing edge. This allows up to a maximum of 2 clocks with programmable polarity for input logic macrocells 415B4. A total of 34 different clocks are available to the macrocells of this invention. With a flexible macrocell structure and a flexible clocking scheme, PLD 215 allows system designers to replace large amounts of random TTL logic in a single package. The asynchronous clock pins, if not utilized as clock sources, are available as input pins to the switch matrix.

I/O macrocell 413B4 (FIG. 63) of PLD 215 is simply a three-state element with the input terminal coupled to the output terminal of polarity control multiplexer 507 of output logic macrocell 412B4 and the output terminal connected to an I/O pin 403B4. The control terminal of the three-state element is driven by an individual output enable product term from the programmable product term array 410B4. Output logic macrocell 412B4 is decoupled and coupled to I/O pin 403B4 by I/O macrocell 413B4. I/O macrocell 413B4 provides an output signal to I/O pin 403B4 and also sends the output signal to centralized switch matrix 401B4 by a dedicated internal feedback line.

Since the output logic macrocells are decoupled from the I/O pins by the I/O macrocells, when the device is programmed in the combinatorial configuration, the programmable output enable capability of the I/O macrocell can be used to transform the I/O pin into a dedicated input terminal or a dynamically controllable I/O terminal. Once enabled as a dedicated input pin, both the input signals and the registered/latched feedback signal from the input logic macrocell are simultaneously available to switch matrix 401B4.

One major benefit of the I/O macrocell structure of this invention is that I/O macrocell decouples the output logic macrocells from the I/O pins. This decoupling has two major side benefits. First, the decoupling provides dual feedback capability for the switch matrix, and second, the decoupling moves the activity to the switch matrix where it belongs rather than fixing it at the pin. Dual feedback capability is beneficial for applications requiring larger amounts of buried logic such as counters, shift registers, and complex state machines as well as I/O-intense applications requiring large numbers of input pins while still preserving the output logic macrocell functions for buried logic.

The configuration of the switch matrix 401A5 is similar to that described above for PLD 210 switch matrix 401B1. Switch matrix 401B4 routes 22 signals to each programmable logic block 402B4. The 22 signals are derived from a maximum of 102 global signals consisting of six dedicated input signals, 32 I/O pin feedback signals, 32 output logic macrocell feedback signals, and 32 input logic macrocell feedback signals.

For ease of representation, programmable logic blocks 402B4-1, 402B4-2, 402B4-3, and 402B4-4, are represented as blocks "A", "B", "C", and "D", respectively for the switch matrix description. Similarly, logic macrocell 412B4-1-1 feedback signal becomes "A0", input logic macrocell 415B4-1-1 feedback signal becomes "A1", logic macrocell 412B4-1-8 feedback signal becomes "A14", and input logic macrocell 415B4-1-8 becomes "A15". Thus, the logic macrocells feedback signals in block 402B4-1 are identified as AO, A2, . . . , A14 and the input logic macrocell feedback signals are identified as A1, A3, . . . , A15. The other logic blocks are similarly renumbered so that even numbers are output logic macrocells and odd numbers are input logic macrocells. The I/O pin feedback signal associated with the output logic macrocell is represented by the macrocell number followed by a carat " ". Dedicated input pins 404B4 are numbered I0 through I1 respectively.

In one embodiment, the 102 signals are grouped into 12 signal bands and one signal from each band is an input signal to one of the 12:1 multiplexers of switch matrix 401B4. The band structure for PLD 215 is the same as for PLD 210 and so is illustrated in Table 7. FIG. 43 illustrates graphically the twelve bands with each band having 8.5 signals. The output line from the band is an input line to a 12:1 multiplexer. The signals have been grouped in bands to maximize routability and to ease the layout of PLD 215. Notice that the signal sources in a band are appropriately rotated to allow both the output and input logic macrocell feedback and the corresponding I/O feedback to be available for each programmable logic block. This rotation allows the buried register capability without increasing the array size and is one of the important features of this invention.

FIGS. 44A to 44C illustrate the actual switch matrix signal patterns for all four programmable logic blocks 402B4 of PLD 215 as well as PLD 210. The columns in FIGS. 44A to 44C are the signals in the band which are rotated within the column, as described above, and each row is the input signals to a 12 to 1 multiplexer that provides the input signal on the input line indicated in the left hand column. Note, for ease of representation FIGS. 44A to 44C includes the input line column in each figure. However, only a single input signal is provided by each row of the table shown in the four figures.

According to the principles of this invention, the 22 input signals for each asynchronous programmable logic block 402B4-i may be unique or the same for all four blocks. This allows PLD 215 to function either as a monolithic array with a maximum of 22 input signals, or four separate relatively independent split-arrays with a total maximum number of 88 input signals out of a possible 102 signals.

Thus, as described above, programmable logic device 215 of this invention has a plurality of programmable connections. The programmable connections are controlled by a multiplicity of electrically erasable cells. The number of cells depend upon the specific implementation, but the number of cells is given in Table 17.

                  TABLE 17                                                         ______________________________________                                         PLD 215                                                                        ______________________________________                                         E.sup.2 cells for the                                                                              4 × 44 × 64 =                                                                  11,264                                         AND-OR array                                                                   E.sup.2 cells for the programmable                                                                 4 × 8 × 6 =                                                                      160                                          logic macrocells                                                               E.sup.2 cells for the programmable                                                                 4 × 8 × 3 =                                                                       96                                          input/output macrocells                                                        E.sup.2 cells for the                                                                              4 × 2 × 8 =                                                                       64                                          logic allocator                                                                E.sup.2 cells for the                                                                              4 × 4 × 22 =                                                                     352                                          switch matrix                                                                  TOTAL                           11,936                                         ______________________________________                                    

Since PLD 215 is derived from the same core as PLD 210, PLD 215 incorporates all of the advantages previously described for the PLD 210 architecture in an asynchronous PLD. Further use of the same core facilitates migration of design and programming software within the family of synchronous and asynchronous PLDs.

Thus, the principles of this invention, in particular the decoupling of the various components in programmable logic block, the symmetric layout and the high speed switch matrix, may be implemented in a wide variety of programmable logic devices. Accordingly, the embodiments described above are only exemplary of the principles of the invention and are not intended to limit the invention to the specific embodiments disclosed. 

I claim:
 1. An integrated circuit having a plurality of input/output (I/O) pins comprising:a plurality of asynchronous programmable logic blocks, each asynchronous programmable logic block having a plurality of input lines and a plurality of output lines; programmable switch interconnection means, operatively coupled to each of said asynchronous programmable logic blocks, for receiving signals on said pluralities of output lines from said plurality of asynchronous programmable logic blocks and for providing input signals to said pluralities of input lines of said plurality of asynchronous programmable logic blocks, wherein each asynchronous programmable logic block includes:programmable array means, operatively coupled to said programmable switch interconnection means, for (i) receiving a plurality of input signals only from said plurality of asynchronous programmable logic block input lines; (ii) generating a plurality of logic output signals in response to said plurality of input signals; and (iii) generating a plurality of control signals in response to said plurality of input signals a plurality of programmable output logic macrocell means, each programmable output logic macrocell means, operatively coupled to said programmable switch interconnection means, having at least one input line, and output line, and a control line wherein said control line is driven by one of said plurality of control signals; logic allocator means, operatively coupled to said programmable array means and selectively operatively coupled to and decoupled from each of said plurality of programmable logic macrocell means, for steering said plurality of output signals of said programmable array means to selected input lined of said plurality of programmable output logic macrocell means and for decoupling said unselected input lines of said plurality of programmable output logic macrocell means from said programmable array means; a plurality of programmable input/output (I/O) macrocells means, each I/O macrocell means, connected to one of said I/O pins, and to the output line of one of said programmable output logic macrocell means, for selectively connecting and disconnecting said programmable output logic macrocell means output line to said I/O pin; and a plurality of programmable input logic macrocell means, each programmable input logic macrocell means, operatively coupled to said programmable switch interconnection means and to an I/O pin, having an input line and an output line wherein said input line is connected to said I/O pin and said output line is connected to said programmable switch interconnection means.
 2. An integrated circuit as in claim 1 wherein each of said programmable output logic macrocell means comprises:programmable storage means, operatively coupled to said programmable output logic macrocell means input line, having an input terminal and an output terminal; first programmable means, operatively coupled to said programmable output logic macrocell means input line and to said output terminal of said programmable storage means, and having an output line, for coupling therethrough to the output line of said first programmable means a signal driven by a signal on said input line or a signal from said programmable storage means wherein said first programmable means output line is connected to said programmable switch interconnection means; and means, operatively coupled to said programmable storage means and to said programmable output logic macrocell means input line, for controlling the polarity of a logic signal;wherein in a first mode of operation, said polarity control means generates a first output signal in response to an input signal; and in a second mode of operation, said polarity control means generates a second output signal in response to said input signal and said second output signal is the inverse of said first output signal.
 3. An integrated circuit as in claim 2 wherein said polarity control means further comprises:second programmable means having (i) an input terminal connected to said first programmable means output line, (ii) a signal inverting input terminal connected to said first programmable means output line, and (iii) an output line, said second programmable means for coupling therethrough to the output line of said second programmable means one of a signal on the output line of said first programmable means and an inverse of the signal on the output line of said first programmable means wherein said second programmable means output line is said output line of said programmable output logic macrocell.
 4. An integrated circuit as in claim 2, each output logic macrocell means further comprising:a multiplicity of input lines that include said at least one input line; and logic gate means, operatively connected to said multiplicity of input lines, having an output line connected to said input terminal of said programmable storage means.
 5. An integrated circuit as in claim 2 wherein said programmable storage means comprises a programmable storage element configurable as any one of the group consisting of a D-type flip-flop, a T-type flip-flop and a latch.
 6. An integrated circuit as nn claim 5 wherein said programmable storage element includes an asynchronous reset terminal.
 7. An integrated circuit as in claim 6 wherein said asynchronous reset terminal is connected to a line driven by one of said programmable array means, plurality of control output signals.
 8. An integrated circuit as in claim 5 wherein said programmable storage element includes an asynchronous preset terminal.
 9. An integrated circuit as in claim 8 wherein said asynchronous reset terminal is connected to a line driven by one of said programmable array means' plurality of control output signals.
 10. An integrated circuit as in claim 2, wherein said programmable storage means has a clock terminal.
 11. An integrated circuit as in claim 10, each of said programmable output logic macrocell means further comprising:programmable clock multiplexer means having a multiplicity of input terminals and an output terminal connected to said programmable storage means clock terminal, said programmable clock multiplexer means in response to an input select signal passing therethrough a signal on a selected input terminal to said output terminal; and means, operatively coupled to said programmable clock multiplexer means, for providing said input select signal.
 12. An integrated circuit as in claim 11 further comprising a plurality of dedicated input pins.
 13. An integrated circuit as in claim 12 whereina first terminal of said multiplicity of programmable clock multiplexer means' input terminals is connected to one of said dedicated input pins; and a second terminal of said multiplicity of programmable clock multiplexer means' input terminals is connected to a line driven by one of said programmable array means' plurality of control output signals.
 14. An integrated circuit as in claim 13 whereina third terminal of said multiplicity of programmable clock multiplexer means' input terminals is a signal inverting terminal and is connected to one of said dedicated input pins; and a fourth terminal of said multiplicity of programmable clock multiplexer means' input terminals is a signal inverting terminal and is connected to a line driven by one of said programmable array means' plurality of control output signals.
 15. An integrated circuit as in claim 2, said programmable I/O macrocell means further comprising:means for selectively providing an enable signal; and means, operatively connected to the output line of the programmable output logic macrocell means, to one of said pins, and to the enable signal providing means, for selectively providing said signal from said polarity control means to said pin wherein said providing means passes said signal from said polarity control means therethrough only upon receiving said enable signal.
 16. An integrated circuit as in claim 15 wherein said means for selectively providing an enable signal further comprises:a line driven by one of said plurality of programmable array means, control output signals.
 17. An integrated circuit as in claim 1 wherein each of said programmable input logic macrocell means comprises:programmable storage means, operatively coupled to an I/O pin, having an input terminal and an output terminal.
 18. An integrated circuit as in claim 17 wherein said programmable storage means comprises a programmable storage element configurable as any one of the group consisting of a D-type flip-flop and a latch.
 19. An integrated circuit as in claim 18, wherein said programmable storage element has a clock terminal.
 20. An integrated circuit as in claim 19, each of said programmable output logic macrocell means further comprising:programmable clock multiplexer means having a multiplicity of input terminals and an output terminal connected to said programmable storage element clock terminal, said programmable clock multiplexer means in response to an input select signal passing therethrough a signal on a selected input terminal to said output terminal; and means, operatively coupled to said programmable clock multiplexer means, for providing said input select signal.
 21. An integrated circuit as in claim 20 further comprising a plurality of dedicated input pins.
 22. An integrated circuit as in claim 21 whereina first terminal of said multiplicity of programmable clock multiplexer means' input terminals is connected to one of said dedicated input pins; and a second terminal of said multiplicity of programmable clock multiplexer means' input terminals is connected to another of said dedicated input pins.
 23. An integrated circuit as in claim 22 whereina third terminal of said multiplicity of programmable clock multiplexer means' input terminals is a signal inverting terminal and is connected to said one of said dedicated input pins; and a fourth terminal of said multiplicity of programmable clock multiplexer means' input terminals is a signal inverting terminal and is connected to said another of said dedicated input pins.
 24. An integrated circuit, as in claim 1, wherein:said logic allocator means comprises a multiplicity of router means, each of said router means having a multiplicity of output lines and a multiplicity of input lines, said router means for coupling signals on said multiplicity of input lines therethrough to a selected output line in said multiplicity of output lines; wherein each router input line is connected to a output line from said programmable logic array; and each router output line is connected to an input line of one of said programmable output logic macrocell means.
 25. An integrated circuit, as in claim 24, wherein each of said router means further comprises:logic gate means connected to said multiplicity of router input lines and having an output line; demultiplexing means having an input terminal connected to said output line of said logic gate means and a multiplicity of outline lines;wherein said demultiplexing means in response to an input select signal passes therethrough a signal on said input terminal to a selected output line in said multiplicity of output lines, and said demultiplexing means multiplicity of output lines are said router means multiplicity of output lines; and means, operatively coupled to said demultiplexing means, for providing said input select signal.
 26. An integrated circuit as in claim 1 wherein each of said asynchronous programmable logic blocks is identical.
 27. An integrated circuit as in claim 26 wherein said identical asynchronous programmable logic blocks are arranged symmetrically around said programmable switch interconnection means.
 28. An integrated circuit, as in claim 1, wherein:said programmable switch interconnection means comprises a multiplicity of multiplexing means, each of said multiplexing means having a multiplicity of input lines and an output line, and each of said multiplexing means in response to an input select signal, passing therethrough a signal on a selected input line to the output line; and means for providing an input select signal to each of the multiplicity of multiplexing means.
 29. An integrated circuit as in claim 1, said programmable switch interconnection means having a fixed path independent delay time for any path between an input terminal and an output terminal of said programmable switch interconnection means.
 30. An integrated circuit as in claim 29 wherein said delay time through said programmable switch interconnection means for connecting one of said asynchronous programmable logic blocks to another of said asynchronous programmable logic blocks is in the range of about 1 to 2 nanoseconds.
 31. An integrated circuit as in claim 1, said programmable switch interconnection means having approximately the same time delay for all signals passing through said programmable switch interconnection means irrespective of the signals origin.
 32. A method of using the core of a synchronous programmable logic device (PLD) to form an asynchronous PLD wherein said synchronous PLD includes (i) a plurality of input/output pins; (ii) a plurality of programmable logic blocks, each programmable logic block having a plurality of input lines and a plurality of output lines; (iii) programmable switch interconnection means, operatively coupled to each of said programmable logic blocks, for receiving signals on said pluralities of output lines from said plurality of programmable logic blocks and for providing input signals to said pluralities of input lines of said plurality of programmable logic blocks and further wherein each programmable logic block includes: (a) programmable array means, operatively coupled to programmable switch interconnection means, having a plurality of product terms; (b) a plurality of programmable output logic macrocell means; (c) a plurality of programmable buried logic macrocell means; and (d) a plurality of input/output(I/O) macrocell means wherein the number of logic product terms in said programmable array means is a predetermined number multiplied by the sum of the plurality of programmable output logic macrocell means and the plurality of programmable buried logic macrocell means so that each of the logic macrocell means has at least the predetermined number of product terms available for logic operations, said method comprising the steps of:converting said plurality of programmable buried logic macrocell means to a plurality of programmable input logic macrocell means; and using at least one of the predetermined number of logic product terms available to a programmable buried logic macrocell as a control product term for one of said programmable output logic macrocells.
 33. The method of claim 32 wherein a first subset of said predetermined number of logic product terms is control product terms of one of said programmable output logic macrocells.
 34. The method of claim 33 wherein a second subset of said predetermined number of logic product terms is a control product term of one of said I/O macrocell means.
 35. An integrated circuit comprising:a plurality of asynchronous programmable circuits wherein each asynchronous programmable circuit includes a plurality of input lines and a plurality of output lines; and programmable interconnection means, operatively coupled to each of said asynchronous programmable circuits, for receiving signals on said pluralities of output lines from said plurality of asynchronous programmable circuits and for providing input signals to said pluralities of input lines of said plurality of asynchronous programmable circuits;wherein each of said plurality of asynchronous programmable circuits receives input signals only on the plurality of input lines driven by said programmable interconnection means so that all asynchronous programmable circuit input signals irrespective of their origin are routed through said programmable interconnection to the asynchronous programmable circuit.
 36. The integrated circuit of claim 35 wherein said programmable interconnect means comprises programmable multiplexers means connected to said pluralities of input lines and to said pluralities of output lines so that the time delay through said programmable interconnect means for all signals irrespective of their origin is a uniform fixed time delay.
 37. The integrated circuit of claim 36 further wherein the size of said programmable multiplexer means give said integrated circuit a routability factor of at least 2.5. 